PCI2040 datasheet(34/79 Pages) TI2

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4−3

4.3

PCI Command Register

The system software accesses the status and command registers for error recovery, diagnostic, and control. This

Bit

Name

PCI command

Type

Default

PCI command

Type:

Read-only, Read/Write

Offset:

04h

Default:

0000h

Table 4−3. PCI Command Register

BIT

FIELD NAME

TYPE

DESCRIPTION

15−10

RSVD

Reserved. Bits 15−10 return 0s when read.

FBB−EN

Fast back-to-back (FBB) enable. This bit controls whether or not the device is allowed to perform

back-to-back capability for bus master transaction. This bit is hardwired to 0 and indicates that FBB

transfers are not supported by PCI2040.

SERR_EN

System error (SERR) enable. This bit is an enable for the output driver on the SERR pin. If this bit is

cleared and a system error condition is set inside PCI2040, then the error signal will not appear on the

external SERR pin.

STEP_EN

Address/data stepping control. This bit indicates whether or not the device performs address stepping.

Since the PCI2040 does not require address stepping, this bit is hardwired to 0.

PERR_EN

Parity error response enable. This bit controls whether or not the device responds to detected parity

errors. If this bit is set, then the PCI2040 responds normally to parity errors. If this bit is cleared, then

the PCI2040 ignores detected parity errors.

VGA_EN

VGA palette snoop. This bit is not applicable for PCI2040 and is hardwired to a 0.

MWI_EN

Memory write and invalidate enable. This bit enables the device to use the memory write and invalidate

command. Since the PCI2040 does not support MWI but uses MW instead, this bit is hardwired to 0.

Special

Special cycle. This bit controls the device’s response to special cycle commands. Since PCI2040 does

not monitor any special commands, this bit is set to 0.

MAST_EN

Bus master control. This bit allows a PCI device to function as a bus master. This bit is always 0 indicating

PCI2040 does not support PCI mastering.

MEM_EN

Memory space enable. This bit enables the device to respond to memory accesses to any of the defined

base address memory regions. If this bit is cleared, then the PCI2040 will not respond to

memory-mapped accesses.

IO_EN

I/O space control. This bit enables the device to respond to I/O accesses within its defined base address

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