PCI2040 datasheet(32/79 Pages) TI2

32 / 79 page

4−1

4 PCI2040 Programming Model

This section describes the PCI2040 PCI configuration registers that make up the 256-byte PCI configuration header.

A brief description is provided for each register, followed by the register offset and a default state for each register.

The bit table also has reserved fields that contain read-only reserved bits. These bits return 0s when read.

4.1

PCI Configuration Registers

The PCI2040 is a device that interfaces the PCI bus to the 8-bit or 16-bit HPI port of Texas Instruments C54x or C6x

family of DSP processors. The configuration header is compliant with the PCI Local Bus Specification.

The configuration header is compliant with the PCI Local Bus Specification as a type 0 bridge header, and is PC98/99

compliant as well. Table 4−1 shows the PCI configuration header, which includes both the predefined portion of the

configuration space and the user-definable registers.

Table 4−1. PCI Configuration Registers

OFFSET

Device ID

Vendor ID

00h

Status

Command

04h

Class code

Revision ID

08h

BIST

Header type

Latency timer

Cache line size

0Ch

HPI CSR memory base address

10h

Control space base address

14h

GPBus base address

18h

Reserved

1Ch

Reserved

20h

Reserved

24h

Reserved

28h

Subsystem ID

Subsystem vendor ID

2Ch

Reserved

30h

Reserved

Capability pointer

34h

Reserved

38h

Max_Lat

Min_GNT

Interrupt pin

Interrupt line

3Ch

Reserved

40h

GPIO output data

GPIO direction control

GPIO input data

GPIO select

44h

Reserved

GPIO interrupt type

48h

Diagnostic

Reserved

Miscellaneous control

4Ch

Power management capabilities

PM next-item pointer

PM capability ID

50h

Reserved

PM control/status

54h

HPI CSR I/O base address

58h

Reserved

HS_CSR

HS next-item pointer

HS capability ID

5Ch

Reserved

60h

Reserved

64h−FFh

NOTE: Optional registers not implemented for PCI2040 return 0s when read.

PCI2040 Datasheet(PDF) 32 Page - Texas Instruments

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