PCI2040 datasheet(49/79 Pages) TI2

49 / 79 page

4−18

4.31 Power Management Control/Status Register

The power management control/status register determines and changes the current power state of the PCI2040. The

contents of this register are not affected by the internally generated reset caused by the transition from the D3hot to

D0 state. All PCI registers will be reset as a result of a D3hot-to-D0 state transition. TI specific registers, PCI power

management registers, and the legacy base address register are not reset.

Bit

Name

Power management control/status

Type

RCU

Default

Power management control/status

Type:

Read/Clear/Update/Write

Offset:

54h

Default:

0000h

Table 4−16. Power Management Control/Status Register

BIT

FIELD NAME

TYPE

DESCRIPTION

PME_STS

RCU

PME status. This bit is set when the PME signal is asserted, independent of the state of bit 8 (PME_EN).

This bit is cleared by a write back of 1, and this also clears the PME signal if PME was asserted. Writing

a 0 to this bit has no effect. This bit will NOT be cleared by the assertion of PCI_RST. It will only be cleared

by the assertion of GRST.

14−13

DATASCALE

Data scale. This two-bit field returns 0s when read.

12−9

DATASEL

Data select. This four-bit field returns 0s when read.

PME_EN

PME enable. This bit enables the function to assert PME. If bit 8 is cleared, then assertion of PME is

disabled. Bit 8 is NOT cleared by the assertion of PCI_RST. It is only cleared by the assertion of GRST.

7−2

RSVD

Reserved. Bits 7−2 return 0s when read.

1−0

PWRSTATE

Power state. This two-bit field is used both to determine the current power state of a function, and to set

the function into a new power state. This field is encoded as:

00 = D0

01 = D1

10 = D2

11 = D3hot

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