PCI2040 datasheet(39/79 Pages) TI2

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4.12 Control Space Base Address Register

The control space base address register allows the host to map the PCI2040’s 32K bytes of control space into host

memory.

Bit

Name

Control space base address

Type

Default

Bit

Name

Control space base address

Type

Default

Control space base address

Type:

Read-only, Read/Write

Offset:

14h

Default:

0000 0000h

Table 4−6. Control Space Base Address Register

BIT

FIELD NAME

TYPE

DESCRIPTION

31−15

AVAIL_ADD

Available address bits. Bits 31−15 allow the host to map the PCI2040’s 32K bytes of control space into

memory. See Sections 3.5.2, DSP Chip Selects, and 3.5.3, HPI Register Access Control, for details

on addressing the control space.

14−4

RSVD

Reserved. Bits 14−4 return 0s when read.

PREFETCHABLE

Prefetchable. This bit is hardwired to 0 in the PCI2040. The control space is not prefetchable.

2−1

TYPE

Type. Bits 2 and 1 indicate the size of the base address and how it can be mapped into the host memory.

These bits are hardwired to 00 in the PCI2040 to indicate that a 32-bit base address register is used

which can be located anywhere in memory.

MEM_IND

Memory space indicator. This bit indicates whether the base address maps into the host’s memory or

I/O space. This bit is hardwired to 0 in the PCI2040 to indicate that the control space is

memory-mapped.

PCI2040 Datasheet(PDF) 39 Page - Texas Instruments

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