S29GL032A datasheet(59/95 Pages) SPANSION

59 / 95 page

September 10, 2007 S29GL-A_00_A11

S29GL-A

Data

She e t

10. Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed

by the address of the sector to be erased, and the sector erase command. Table 10.2 on page 61 and

Table 10.1 on page 62 shows the address and data requirements for the sector erase command sequence.

The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm

automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase.

The system is not required to provide any controls or timings during these operations.

After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period,

additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may

be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between

these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase address and

command following the exceeded time-out may or may not be accepted. It is recommended that processor

interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be

re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or

Erase Suspend during the time-out period resets the device to the read mode. Note that the Secured

Silicon Sector, autoselect, and CFI functions are unavailable when an erase operation is in progress.

The system must rewrite the command sequence and any additional addresses and commands.

The system can monitor DQ3 to determine if the sector erase timer has timed out (See DQ3: Sector Erase

Timer on page 67). The time-out begins from the rising edge of the final WE# pulse in the command

sequence.

When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses

are no longer latched. The system can determine the status of the erase operation by reading DQ7, DQ6, or

DQ2 in the erasing sector. Refer to Write Operation Status on page 63 for information on these status bits.

Once the sector erase operation begins, only the Erase Suspend command is valid. All other commands are

ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the

sector erase command sequence should be reinitiated once the device returns to reading array data, to

ensure data integrity.

Figure 10.1 illustrates the algorithm for the erase operation. Refer to Table 16.5 on page 76 for parameters,

and Figure 16.7 on page 80 for timing diagrams.

Figure 10.1 Erase Operation

Notes

1. See Table 10.2 on page 61 and Table 10.1 on page 62 for program command sequence.

2. See DQ3: Sector Erase Timer on page 67 for information on the sector erase timer.

START

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Data = FFh?

Yes

Erasure Completed

Embedded

Erase

algorithm

in progress

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