S29GL032A datasheet(66/95 Pages) SPANSION

66 / 95 page

S29GL-A

S29GL-A_00_A11 September 10, 2007

Da ta

Sh e e t

Figure 10.4 Toggle Bit Algorithm

Note

The system should recheck the toggle bit even if DQ5 = 1 because the toggle bit may stop toggling as DQ5 changes to 1. See DQ6: Toggle

Bit I on page 65 and DQ2: Toggle Bit II on page 66 for more information.

10.7

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that

is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is

valid after the rising edge of the final WE# pulse in the command sequence.

DQ2 toggles when the system reads at addresses within those sectors that were selected for erasure. (The

system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the

sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is

actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus,

both status bits are required for sector and mode information. Refer to Table 10.2 on page 68 to compare

outputs for DQ2 and DQ6.

Figure 10.4 on page 66 shows the toggle bit algorithm in flowchart form, and DQ2: Toggle Bit II on page 66

explains the algorithm. See also RY/BY#: Ready/Busy# on page 64. Figure 16.9 on page 81 shows the

toggle bit timing diagram. Figure 16.10 on page 81 shows the differences between DQ2 and DQ6 in graphical

form.

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle?

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Read DQ7–DQ0

Toggle Bit

= Toggle?

Read DQ7–DQ0

Twice

Read DQ7–DQ0

S29GL032A Datasheet(PDF) 66 Page - SPANSION