S29GL032A datasheet(67/95 Pages) SPANSION

67 / 95 page

September 10, 2007 S29GL-A_00_A11

S29GL-A

Data

She e t

10.8

Reading Toggle Bits DQ6/DQ2

Refer to Figure 10.4 on page 66 for the following discussion. Whenever the system initially begins reading

toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.

Typically, the system would note and store the value of the toggle bit after the first read. After the second

read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling,

the device completed the program or erase operation. The system can read array data on DQ7–DQ0 on the

following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the

system also should note whether the value of DQ5 is high (see DQ5: Exceeded Timing Limits on page 67). If

it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have

stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device successfully

completed the program or erase operation. If it is still toggling, the device did not completed the operation

successfully, and the system must write the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not

gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles,

determining the status as described in the previous paragraph. Alternatively, it may choose to perform other

system tasks. In this case, the system must start at the beginning of the algorithm when it returns to

determine the status of the operation (top of Figure 10.4 on page 66).

10.9

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program, erase, or write-to-buffer time exceeded a specified internal pulse count

limit. Under these conditions DQ5 produces a 1. indicating that the program or erase cycle was not

successfully completed.

The device may output a 1 on DQ5 if the system tries to program a 1 to a location that was previously

programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the device

halts the operation, and when the timing limit is exceeded, DQ5 produces a 1.

In all these cases, the system must write the reset command to return the device to the reading the array (or

to erase-suspend-read if the device was previously in the erase-suspend-program mode).

10.10 DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to determine whether or not

erasure began. (The sector erase timer does not apply to the chip erase command.) If additional sectors are

selected for erasure, the entire time-out also applies after each additional sector erase command. When the

time-out period is complete, DQ3 switches from a 0 to a 1. If the time between additional sector erase

commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See

Sector Erase Command Sequence on page 59.

After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device accepted the command sequence, and then read DQ3. If DQ3 is 1, the

Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the

erase operation is complete. If DQ3 is 0, the device accepts additional sector erase commands. To ensure

the command is accepted, the system software should check the status of DQ3 prior to and following each

subsequent sector erase command. If DQ3 is high on the second status check, the last command might not

have been accepted.

Table 10.2 on page 68 shows the status of DQ3 relative to the other status bits.

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