TLC1514, TLC1518

5-V, 10-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN

SLAS252 – DECEMBER 1999

20

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

recommended operating conditions (continued)

MIN

NOM

MAX

UNIT

Transition time, for FS, SCLK, SDI, tt(CLK)

0.5

SCLK

Setup time, CS falling edge before SCLK rising edge (FS=1) or before SCLK falling edge (when FS is active),

tsu(CS-SCLK)

0.5

SCLK

Hold time, CS rising edge after SCLK rising edge (FS=1) or after SCLK falling edge (when FS is active),

th(SCLK-CS)

5

ns

Delay time, delay from CS falling edge to FS rising edge, td(CSL-FSH)

0.5

7

SCLKs

Delay time, delay time from 16th SCLK falling edge to CS rising edge (FS is active), td(SCLK16F-CSH)

0.5

SCLKs

Setup time, FS rising edge before SCLK falling edge, tsu(FSH-SCLKF)

0.5

SCLKs

Hold time, FS hold high after SCLK falling edge, th(FSH-SCLKF)

0.5

SCLKs

Pulse width, CS high time, twH(CS)

100

ns

SCLK cycle time, VCC = 2.7 V to 3.6V, tc(SCLK)

67

ns

SCLK cycle time, VCC = 4.5 V to 5.5V, tc(SCLK)

50

ns

Pulse width, SCLK low time, twL(SCLK)

20

30

ns

Pulse width, SCLK high time, twH(SCLK)

20

30

ns

Setup time, SDI valid before falling edge of SCLK (FS is active) or the rising edge of SCLK (FS=1),

tsu(DI-SCLK)

25

ns

Hold time, SDI hold valid after falling edge of SCLK (FS is active) or the rising edge of SCLK (FS=1),

th(DI-SCLK)

5

ns

Delay time, delay from CS falling edge to SDO valid, td(CSL-DOV)

1

25

ns

Delay time, delay from FS falling edge to SDO valid, td(FSL-DOV)

1

25

ns

Delay time, delay from SCLK rising edge (FS is active) or SCLK falling edge (FS=1) SDO valid, td(CLK-DOV)

1

25

ns

Delay time, delay from CS rising edge to SDO 3-stated, td(CSH-DOZ)

1

25

ns

Delay time, delay from 16th SCLK falling edge (FS is active) or the 16th rising edge (FS=1) to EOC falling

edge, td(CLK-EOCL)

1

25

ns

Delay time, delay from EOC rising edge to SDO 3-stated if CS is low, td(EOCH-DOZ)

1

50

ns

Delay time, delay from 16th SCLK rising edge to INT falling edge (FS =1) or from the 16th falling edge SCLK

to INT falling edge (when FS active), td(SCLK-INTL)

3.5

µs

Delay time, delay from CS falling edge to INT rising edge, td(CSL-INTH)

1

50

ns

Delay time, delay from CS rising edge to CSTART falling edge, td(CSH-CSTARTL)

100

ns

Delay time, delay from CSTART rising edge to EOC falling edge, td(CSTARTH-EOCL)

1

50

ns

Pulse width, CSTART low time, twL(CSTART)

0.8

µs

Delay time, delay from CS rising edge to EOC rising edge, td(CSH-EOCH)

1

50

ns

Delay time, delay from CSTART rising edge to CSTART falling edge, td(CSTARTH-CSTARTL)

3.6

µs

Delay time, delay from CSTART rising edge to INT falling edge, td(CSTARTH-INTL)

3.5

µs

Operating free-air temperature, TA

TLC1514I/TLC1518I

–40

85

_C

NOTE 2: This is the time required for the clock input signal to fall from VIH max or to rise from VILmax to VIHmin. In the vicinity of normal room

temperature, the devices function with input clock transition time as slow as 1

µs for remote data-acquisition applications where the

sensor and A/D converter are placed several feet away from the controlling microprocessor.