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AFE5805 Datasheet(PDF) 24 Page - Texas Instruments |
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AFE5805 Datasheet(HTML) 24 Page - Texas Instruments |
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24 / 53 page  AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.com Table 2. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE (1) (2) (3) (4) (continued) ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME DESCRIPTION DEFAULT X X X X GAIN_CH4<3:0> Programmable gain channel 4. 0dB gain X X X X GAIN_CH3<3:0> Programmable gain channel 3. 0dB gain 2A X X X X GAIN_CH2<3:0> Programmable gain channel 2. 0dB gain X X X X GAIN_CH1<3:0> Programmable gain channel 1. 0dB gain X X X X GAIN_CH5<3:0> Programmable gain channel 5. 0dB gain X X X X GAIN_CH6<3:0> Programmable gain channel 6. 0dB gain 2B X X X X GAIN_CH7<3:0> Programmable gain channel 7. 0dB gain X X X X GAIN_CH8<3:0> Programmable gain channel 8. 0dB gain Single- 1 1 X DIFF_CLK Differential clock mode. ended clock Enables the duty-cycle 1 1 X EN_DCC Disabled correction circuit. External 42 Drives the external reference reference 1 1 X EXT_REF_VCM mode through the VCM pin. drives REFT and REFB Controls the phase of LCLK 1 1 X X PHASE_DDR<1:0> 90 degrees output relative to data. 0 X PAT_DESKEW Enables deskew pattern mode. Inactive 45 X 0 PAT_SYNC Enables sync pattern mode. Inactive Binary two's complement Straight 1 1 X BTC_MODE format for ADC output. offset binary Serialized ADC output comes LSB-first 1 1 X MSB_FIRST out MSB-first. output Enables SDR output mode DDR output 1 1 X EN_SDR (LCLK becomes a 12x input 46 mode clock). Controls whether the LCLK Rising edge rising or falling edge comes in of LCLK in 1 1 1 1 FALL_SDR the middle of the data window middle of when operating in SDR output data window mode. SUMMARY OF FEATURES POWER IMPACT (Relative to Default) FEATURES DEFAULT SELECTION AT fS = 50MSPS ANALOG FEATURES Internal or external reference N/A Pin Internal reference mode takes approximately 20mW more power on AVDD1 (driven on the REFT and REFB pins) External reference driven on the CM pin Off Register 42 Approximately 8mW less power on AVDD1 Duty cycle correction circuit Off Register 42 Approximately 7mW more power on AVDD1 With zero input to the ADC, low-frequency noise suppression causes digital switching Low-frequency noise suppression Off Register 14 at fS/2, thereby increasing LVDD power by approximately 5.5mW/channel Single-ended or differential clock Single-ended Register 42 Differential clock mode takes approximately 7mW more power on AVDD1 Power-down mode Off Pin and register 0F Refer to the Power-Down Modes section in the Electrical Characteristics table DIGITAL FEATURES Programmable digital gain (0dB to 12dB) 0dB Registers 2A and 2B No difference Straight offset or BTC output Straight offset Register 46 No difference LVDS OUTPUT PHYSICAL LAYER LVDS internal termination Off Register 12 Approximately 7mW more power on AVDD1 LVDS current programmability 3.5mA Register 11 As per LVDS clock and data buffer current setting LVDS OUTPUT TIMING LSB- or MSB-first output LSB-first Register 46 No difference DDR or SDR output DDR Register 46 SDR mode takes approximately 2mW more power on LVDD (at fS = 30MSPS) LCLK phase relative to data output Refer to Figure 43 Register 42 No difference 24 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): AFE5805 |
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