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AFE5805 Datasheet(PDF) 34 Page - Texas Instruments |
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AFE5805 Datasheet(HTML) 34 Page - Texas Instruments |
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34 / 53 page ![]() FCLKP LCLKP OUTP PHASE_DDR<1:0>= '00' PHASE_DDR<1:0>= '01' PHASE_DDR<1:0>= '10' PHASE_DDR<1:0>= '11' FCLKP LCLKP OUTP FCLKP LCLKP OUTP FCLKP LCLKP OUTP FCLKP LCLKP OUTP AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.com BIT CLOCK PROGRAMMABILITY The output interface of the AFE5805 is normally a DDR interface, with the LCLK rising edge and falling edge transitions in the middle of alternate data windows. Figure 43 shows this default phase. Figure 43. LCLK Default Phase The phase of LCLK can be programmed relative to the output frame clock and data using bits PHASE_DDR<1:0>. Figure 44 shows the LCLK phase modes. Figure 44. LCLK Phase Programmability Modes 34 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): AFE5805 |
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