AFE5805 datasheet(6/53 Pages) TI2

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AFE5805

SBOS421D – MARCH 2008 – REVISED MARCH 2010

www.ti.com

DIGITAL CHARACTERISTICS

DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level

'0' or '1'. At CLOAD = 5pF

(1), I

OUT = 3.5mA

(2), R

LOAD = 100Ω

(2), and no internal termination, unless otherwise noted.

AFE5805

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUTS

High-level input voltage

1.4

3.3

Low-level input voltage

0.3

High-level input current

Low-level input current(3)

–10

Input capacitance

LVDS OUTPUTS

High-level output voltage

1375

Low-level output voltage

1025

Output differential voltage, |VOD|

350

VOS output offset voltage

(2)

Common-mode voltage of OUTP and OUTM

1200

Output capacitance inside the device,

Output capacitance

from either output to ground

FCLKP and FCLKM

1x (clock rate)

MHz

LCLKP and LCLKM

6x (clock rate)

300

MHz

CLOCK

Clock input rate

MSPS

Clock duty cycle

Clock input amplitude, differential

Sine-wave, ac-coupled

VPP

(VCLKP – VCLKM)

LVPECL, ac-coupled

1.6

VPP

LVDS, ac-coupled

0.7

VPP

Clock input amplitude, single-ended

(VCLKP)

High-level input voltage, VIH

CMOS

2.2

Low-level input voltage, VIL

CMOS

0.6

(1)

CLOAD is the effective external single-ended load capacitance between each output pin and ground.

(2)

IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair.

(3)

Except pin J3 (INT/EXT), which has an internal pull-up resistor (52k

Ω) to 3.3V.

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