16LF1613 datasheet(97/396 Pages) MICROCHIP

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DS40001737B-page 97

PIC12(L)F1612/16(L)F1613

9.1

Independent Clock Source

The WDT can derive its time base from either the 31

kHz LFINTOSC or 31.25 kHz MFINTOSC internal

oscillators, depending on the value of either the

WDTCCS<2:0> configuration bits or the WDTCS<2:0>

bits of WDTCON1. Time intervals in this chapter are

based on a minimum nominal interval of 1 ms. See

Section28.0 “Electrical

Specifications”

for

LFINTOSC and MFINTOSC tolerances.

9.2

WDT Operating Modes

The Watchdog Timer module has four operating modes

controlled by the WDTE<1:0> bits in Configuration

Words. See Table 9-1.

9.2.1

WDT IS ALWAYS ON

When the WDTE bits of Configuration Words are set to

‘11’, the WDT is always on.

WDT protection is active during Sleep.

9.2.2

WDT IS OFF IN SLEEP

When the WDTE bits of Configuration Words are set to

‘10’, the WDT is on, except in Sleep.

WDT protection is not active during Sleep.

9.2.3

WDT CONTROLLED BY SOFTWARE

When the WDTE bits of Configuration Words are set to

‘01’, the WDT is controlled by the SEN bit of the

WDTCON0 register.

WDT protection is unchanged by Sleep. See Table 9-1

for more details.

TABLE 9-1:

WDT OPERATING MODES

9.3

Time-Out Period

The WDTPS bits of the WDTCON0 register set the

time-out period from 1 ms to 256 seconds (nominal).

After a Reset, the default time-out period is two

seconds.

9.4

Watchdog Window

The Watchdog Timer has an optional Windowed mode

that is controlled by the WDTCWS<2:0> Configuration

bits and WINDOW<2:0> bits of the WDTCON1 register.

In the Windowed mode, the CLRWDT instruction must

occur within the allowed window of the WDT period.

Any CLRWDT instruction that occurs outside of this win-

dow will trigger a window violation and will cause a

WDT Reset, similar to a WDT time out. See Figure 9-2

for an example.

The window size is controlled by the WDTCWS<2:0>

Configuration bits, or the WINDOW<2:0> bits of

WDTCON1, if WDTCWS<2:0> = 111.

In the event of a window violation, a Reset will be

generated and the WDTWV bit of the PCON register

will be cleared. This bit is set by a POR or can be set in

firmware.

9.5

Clearing the WDT

The WDT is cleared when any of the following condi-

tions occur:

•Any Reset

•Valid CLRWDT instruction is executed

• Device enters Sleep

• Device wakes up from Sleep

• WDT is disabled

• Oscillator Start-up Timer (OST) is running

• Any write to the WDTCON0 or WDTCON1 registers

9.5.1

CLRWDT

CONSIDERATIONS

(WINDOWED MODE)

When in Windowed mode, the WDT must be armed

before a CLRWDT instruction will clear the timer. This is

performed by reading the WDTCON0 register. Execut-

ing a CLRWDT instruction without performing such an

arming action will trigger a window violation.

See Table 9-2 for more information.

9.6

Operation During Sleep

When the device enters Sleep, the WDT is cleared. If

the WDT is enabled during Sleep, the WDT resumes

counting. When the device exits Sleep, the WDT is

cleared again.

The WDT remains clear until the OST, if enabled, com-

pletes. See Section5.0 “Oscillator Module” for more

information on the OST.

When a WDT time-out occurs while the device is in

Sleep, no Reset is generated. Instead, the device

wakes up and resumes operation. The TO and PD bits

in the STATUS register are changed to indicate the

event. The RWDT bit in the PCON register can also be

used. See Section3.0 “Memory Organization” for

more information.

WDTE<1:0>

SEN

Device

Mode

WDT

Mode

XActive

Awake

Active

Sleep

Disabled

XActive

Disabled

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