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LM73 Datasheet(PDF) 7 Page - Texas Instruments

Part # LM73
Description  LM73-Q1 2.7-V, SOT-23, 11- to 14-Bit Digital Temperature Sensor With 2-Wire Interface
PDF  31 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

LM73 Datasheet(HTML) 7 Page - Texas Instruments

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VIH
VIL
SMBCLK
P
S
VIH
VI
L
SMBDAT
tBUF
tHD;STA
tLOW
tR
tHD;DAT
tHIGH
tF
tSU;DAT
tSU;STA
tSU;STO
P
S
7
LM73-Q1
www.ti.com
SNIS194 – DECEMBER 2016
Product Folder Links: LM73-Q1
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
(1)
The output fall time is measured from (VIH;MIN + 0.15V) to (VIL;MAX - 0.15V).
(2)
Holding the SMBDAT and/or SMBCLK lines Low for a time interval greater than tTIMEOUT will reset the LM73-Q1's SMBus state machine,
setting SMBDAT and SMBCLK pins to a high impedance state.
(3)
Represents the time from VDD reaching the power-on-reset level to the LM73-Q1 communications being functional. After an additional
time equal to one temperature conversion time, valid temperature is available in the Temperature Data Register .
6.7 SMBus Digital Switching Characteristics
Unless otherwise noted, these specifications apply for VDD = 2.7 V to 5.5 V, CL (load capacitance) on output lines = 400 pF.
All limits TA = TJ = 25°C, unless otherwise noted. See Figure 1.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fSMB
SMBus Clock Frequency
No minimum clock
frequency if Time-
Out feature is
disabled.
TA = TJ =TMIN to TMAX
400
kHz
tLOW
SMBus Clock Low Time
TA = TJ =TMIN to TMAX
300
ns
tHIGH
SMBus Clock High Time
TA = TJ =TMIN to TMAX
300
ns
tF;SMB
O
Output Fall Time (1)
CL = 400 pF
IPULL-UP ≤ 3 mA
TA = TJ =TMIN to TMAX
250
ns
tTIMEO
UT
SMBDAT and SMBCLK Time
Low for Reset of Serial Interface
(2)
TA = TJ =TMIN to TMAX
15
45
ms
tSU;DAT
Data In Setup Time to SMBCLK
High
TA = TJ =TMIN to TMAX
100
ns
tHD;DA
TI
Data Hold Time: Data In Stable
after SMBCLK Low
TA = TJ =TMIN to TMAX
0
ns
tHD;DA
TO
Data Hold Time: Data Out Stable
after SMBCLK Low
TA = TJ =TMIN to TMAX
30
ns
tHD;STA
Start Condition SMBDAT Low to
SMBCLK Low (Start condition
hold before the first clock falling
edge)
TA = TJ =TMIN to TMAX
60
ns
tSU;ST
O
Stop Condition SMBCLK High to
SMBDAT Low (Stop Condition
Setup)
TA = TJ =TMIN to TMAX
50
ns
tSU;STA
SMBus Repeated Start-Condition
Setup Time, SMBCLK High to
SMBDAT Low
TA = TJ =TMIN to TMAX
50
ns
tBUF
SMBus Free Time Between Stop
and Start Conditions
TA = TJ =TMIN to TMAX
1.2
µs
tPOR
Power-On Reset Time (3)
TA = TJ =TMIN to TMAX
1
ms
Figure 1. SMBus Communication



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