TPA2012D2 datasheet(33/43 Pages) TI2

33 / 43 page

TPA2026D2

www.ti.com

SLOS649B – MARCH 2010 – REVISED MAY 2016

Product Folder Links: TPA2026D2

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11 Power Supply Recommendations

The TPA2026D2 is designed to operate from an input voltage supply range between 2.5 V and 5.5 V. Therefore

the output voltage range of the power supply should be within this range. The current capability of upper power

must not exceed the maximum current limit of the power switch.

11.1 Power Supply Decoupling Capacitors

The TPA2026D2 requires adequate power supply decoupling to ensure a high efficiency operation with low total

harmonic distortion (THD). Place a low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µF,

within 2 mm of the VDD/VCCOUT pin. This choice of capacitor and placement helps with higher frequency

transients, spikes, or digital hash on the line. In addition to the 0.1-

μF ceramic capacitor, is recommended to

place a 2.2-µF to 10-µF capacitor on the VDD supply trace. This larger capacitor acts as a charge reservoir,

providing energy faster than the board supply, thus helping to prevent any droop in the supply voltage.

12 Layout

12.1 Layout Guidelines

12.1.1 Pad Size

In making the pad size for the WCSP balls, TI recommends that the layout use non solder mask-defined (NSMD)

land. With this method, the solder mask opening is made larger than the desired land area, and the opening size

is defined by the copper pad width. Figure 51 and Table 16 show the appropriate diameters for a WCSP layout.

The TPA2026D2 evaluation module (EVM) layout is shown in Layout Example.

Figure 51. Land Pattern Dimensions

TPA2012D2 Datasheet(PDF) 33 Page - Texas Instruments