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TPA2012D2 Datasheet(PDF) 5 Page - Texas Instruments

Part # TPA2012D2
Description  TPA2026D2 3.2-W/Ch Stereo Class-D Audio Amplifier With Fast Gain Ramp SmartGain™ Automatic Gain Control and Dynamic Range Compression
PDF  43 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

TPA2012D2 Datasheet(HTML) 5 Page - Texas Instruments

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TPA2026D2
www.ti.com
SLOS649B – MARCH 2010 – REVISED MAY 2016
Product Folder Links: TPA2026D2
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
7.5 Electrical Characteristics
at TA = 25°C, VDD = 3.6 V, SDZ = 1.3 V, and RL = 8 Ω + 33 μH (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD
Supply voltage range
2.5
3.6
5.5
V
ISDZ
Shutdown quiescent current
SDZ = 0.35 V, VDD = 2.5 V
0.1
1
µA
SDZ = 0.35 V, VDD = 3.6 V
0.2
1
SDZ = 0.35 V, VDD = 5.5 V
0.3
1
ISWS
Software shutdown quiescent
current
SDZ = 1.3 V, VDD = 2.5 V
35
50
µA
SDZ = 1.3 V, VDD = 3.6 V
50
70
SDZ = 1.3 V, VDD = 5.5 V
75
110
IDD
Supply current
VDD = 2.5 V
3.5
4.5
mA
VDD = 3.6 V
3.7
4.7
VDD = 5.5 V
4.5
5.5
fSW
Class-D switching frequency
275
300
325
kHz
IIH
High-level input current
VDD = 5.5 V, SDZ = 5.8 V
1
µA
IIL
Low-level input current
VDD = 5.5 V, SDZ = –0.3 V
–1
µA
tSTART
Start-up time
2.5 V
≤ VDD ≤ 5.5 V no pop, CIN ≤ 1 μF
5
ms
POR
Power on reset ON threshold
2
2.3
V
POR
Power on reset hysteresis
0.2
V
CMRR
Input common-mode rejection
RL = 8 Ω, Vicm = 0.5 V and Vicm = VDD – 0.8 V,
differential inputs shorted
–70
dB
Voo
Output offset voltage
VDD = 3.6 V, AV = 6 dB, RL = 8 Ω, inputs AC
grounded
2
10
mV
ZOUT
Output impedance in shutdown
mode
SDZ = 0.35 V
2
k
Ω
Gain accuracy
Compression and limiter disabled, Gain = 0 to 30 dB
–0.5
0.5
dB
PSRR
Power supply rejection ratio
VDD = 2.5 V to 4.7 V
–80
dB
7.6 I
2C Timing Requirements
For I
2C Interface Signals Over Recommended Operating Conditions (unless otherwise noted)
MIN
TYP
MAX
UNIT
fSCL
Frequency, SCL
No wait states
400
kHz
tW(H)
Pulse duration, SCL high
0.6
μs
tW(L)
Pulse duration, SCL low
1.3
μs
tSU(1)
Setup time, SDA to SCL
100
ns
th1
Hold time, SCL to SDA
10
ns
t(buf)
Bus free time between stop and start condition
1.3
μs
tSU2
Setup time, SCL to start condition
0.6
μs
th2
Hold time, start condition to SCL
0.6
μs
tSU3
Setup time, SCL to stop condition
0.6
μs
(1)
Dissipations ratings are for a 2-side, 2-plane PCB.
7.7 Dissipation Ratings
PACKAGE
TA ≤ 25°C
DERATING FACTOR
TA = 70°C
TA = 85°C
16-ball WCSP(1)
1.25 W
10 mW/°C
0.8 W
0.65 W



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