TPS40020

TPS40021

SLUS535D − MARCH 2003 − REVISED JULY 2007

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16

APPLICATION INFORMATION

UDG−03181

VOUT − 1%

1.5

µs

VOUT

4

µs

VDD

0.3 V

0.6 V

500 ns

Transient Comparators Disabled

Transient Comparators Enabled

SS/SD

PWRGD

1.3 V

Figure 8. Transient Comparator Waveforms

Layout Considerations

Successful operation of the TPS4002x family of controllers is dependent upon the proper converter layout and

grounding techniques. High current returns for the SR MOSFET’s source, input capacitance, output

capacitance, PVDD capacitance, and input bypass capacitors (if applicable), should be kept on a single ground

plane or wide trace connected to the PGND (pin10) through a short wide trace. Control components connected

to signal ground, as well as the PowerPad thermal pad, should be connected to a single ground plane connected

to SGND (Pin 8) through a short trace. SGND and PGND should be connected at a single point using a narrow

trace.

Proper operation of Predictive Gate Drive

 technology and IZERO functions are dependent upon detecting

low-voltage thresholds on the SW node. To ensure that the signal at the SW pin accurately represents the

voltage at the main switching node, the connection from SW (pin 14) to the main switching node of the converter

should be kept as short and wide as possible and should ideally be kept on the top level with the power

components. If the SW trace must traverse multiple board layers between the TPS4002x and the main

switching node, multiple vias should be used to minimize the trace impedance.

Gate drive outputs, LDRV and HDRV (pins 11 and 15, respectively) should be kept as short as possible to

minimize inductances in the traces. If the gate drive outputs need to traverse multiple board layers multiple vias

should be used.

Charge pump components, BOOT1, BOOT2, PVDD, and any input bypass capacitors (if required), should be

kept as close as possible to their respective pins. Ceramic bypass capacitors should be used if the input

capacitors are located more than a couple of inches away from the TPS4002X. If a bypass capacitor is not

needed the trace from the input capacitors to VDD (pin2) should be kept as short and wide as possible to

minimize trace impedance. If multiple board layers are traversed multiple vias should be used.

Not Recommended for New Designs