TPS40020

TPS40021

SLUS535D − MARCH 2003 − REVISED JULY 2007

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10

APPLICATION INFORMATION

Synchronous Rectification and Predictive Gate Delay

In a normal buck converter, when the high−side switch turns off, current is flowing in the inductor. Since this

current cannot be stopped immediately a rectifier or catch device is used to give this current a path to flow and

maintain voltage levels at a safe level. This device can be a simple diode or it can be an actively−controlled

transistor if a control signal is available to drive it. The TPS4002X provides a signal to drive an N−channel

MOSFET as a synchronous rectifier. This control signal is carefully coordinated with the drive signal for the

main switch so that there is absolute minimum dead−time between the turn off of one FET and the turn on of

the other. This TI−patented function, predictive gate delay, uses information from the current switching cycle

to adjust the delays for the next cycle virtually eliminating diode conduction while preventing cross−conduction

or shoot through. Figure 2 shows the switch−node voltage waveform for a synchronously rectified buck

converter during the synchronous rectification period. Illustrated are the relative effects of a fixed delay drive

scheme (constant, pre−set delays for the turn−off to turn−on intervals), an adaptive delay drive scheme

(variable delays based on voltages sensed on the current switching cycle) and TI’s predictive delay drive

scheme. Since the diode voltage drop is greater than the conduction drop of the FET, the longer time spent

in diode conduction, the more power dissipated in the rectifier and the lower the efficiency. Also, not shown

in the figure, is the fact that the predictive delay circuit can actually prevent the body diode from becoming

forward biased at all, avoiding reverse recovery and its associated losses. This results in a significant power

savings when the main FET turns on.

The predictive gate drive architecture on the TPS40020/21 requires a minimum pulse width of greater than

150 ns for proper operation. At pulse widths below 150 ns, the low−side FET turn−on could overlap the high−side

FET turn−off leading to cross conduction in the power stage.

UDG−01144

GND

Fixed Delay

Adaptive Delay

Predictive Delay

Channel Conduction

Body Diode Conduction

Figure 2. Switch Node Waveforms for Synchronous Buck Converter

Not Recommended for New Designs