TPS40020

TPS40021

SLUS535D − MARCH 2003 − REVISED JULY 2007

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2

DESCRIPTION (CONTINUED)

The short circuit current detection is programmable through a single resistor, allowing the short circuit current limit

detection threshold to be easily tailored to accommodate different size (RDS(on)) MOSFETs. The short circuit current

function provides pulse-by-pulse current limiting during soft-start and short term transient conditions as well as a fault

counter to handle longer duration short circuit current conditions. If a fault is detected the controller shuts down for

a period of time determined by six (6) consecutive soft-start cycles. The controller automatically retries the output

every seventh (7th) soft-start cycle.

In addition to determining the off time during a fault condition, the soft-start ramp provides a closed loop controlled

ramp of the converter output during startup. Programmability allows the ramp rate to be adjusted for a wide variety

of output L-C component values.

The output voltage transient comparators provide a quick response , first strike, approach to output voltage transients. The

output voltage is sensed through a resistor divider at the OSNS pin. If an overvoltage condition is detected the HDRV gate

drive is shut-off and the LDRV gate drive is turned on until the output is returned to regulation. Similarly, if an output

undervoltage condition is sensed the HDRV gate drive goes to 95% duty cycle to pump the output back up quickly. In either

case, the PowerGood open drain output pulls low to indicate an output voltage out of regulation condition. The PowerGood

output can be daisy-chained to the SS/SD pin or enable pin of other controllers or converters for output voltage sequencing.

The transient comparators can be disabled by simply tying the OSNS pin to VDD.

The TPS4002x can be externally synchronized through the ILIM/SYNC pin up to 1.5

× the free-running frequency. This

allows multiple contollers to be synchronized to eliminate EMI concerns due to input beat frequencies between controllers.

INTERNAL BLOCK DIAGRAM

UDG−02092

VDD

DISABLE

2

BOOT2

13

VDD

9

ILIM/SYNC

1

PWRGD

5

SW

14

COMP

6

PVDD

12

SS/SD

8

LDRV

11

SGND

UVLO

VDD

3

OSNS

4

FB

7

RT

0.719 V

0.659 V

+

0.69 V

OSC

UVLO

PREDICTIVE

GATE

DRIVE(tm)

PWM

LOGIC

CLK

CHARGE

PUMP

BOOT1

16

HDRV

15

PWM

ACTIVE

DRV

VDD

UVLO

FAULT

COUNTER

SOFT

START

FAULT

SS

ACTIVE

DCHG

CLK

−

+

OC

0.28 V

UVLO

ISS

SD

VDD

UVLO

1 V

VDD

SYNC

DRV

PVDD

PGND

10

CURRENT LIMIT

COMPARATOR

+

1.4 V

+

IRT

IRT

SS

Not Recommended for New Designs