DIX4192 datasheet(6/70 Pages) TI2

6 / 70 page

DIX4192-Q1

SBFS041A – JULY 2016 – REVISED APRIL 2017

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Product Folder Links: DIX4192-Q1

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(1)

AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

8.2 ESD Ratings

VALUE

UNIT

V(ESD)

Electrostatic discharge

Human-body model (HBM), per AEC Q100-002(1)

±2000

Charged-device model (CDM), per AEC

Q100-011

All pins

±500

Corner pins (1, 12, 13,

24, 25, 36, 37, and 48)

±750

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

VDD18

1.8-V power-supply voltage

1.65

1.8

1.95

VDD33

3.3-V power-supply voltage

3.3

3.6

VCC

DIR comparator and PLL power-supply voltage

3.3

3.6

VIO

Logic I/O power-supply voltage

1.65

3.3

3.6

Ambient operating temperature

DIX4192I-Q1

–40

°C

DIX4192T-Q1

–40

105

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

8.4 Thermal Information

THERMAL METRIC(1)

DIX4192-Q1

UNIT

PFB (TQFP)

48 PINS

RθJA

Junction-to-ambient thermal resistance

62.0

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

12.8

°C/W

RθJB

Junction-to-board thermal resistance

27.9

°C/W

ψJT

Junction-to-top characterization parameter

0.3

°C/W

ψJB

Junction-to-board characterization parameter

27.6

°C/W

8.5 Electrical Characteristics

all specifications are at TA = 25°C, VDD18 = 1.8 V, VDD33 = 3.3 V, VIO = 3.3 V, and VCC = 3.3 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL I/O CHARACTERISTICS (ALL I/O PINS EXCEPT LINE RECEIVERS AND LINE DRIVER)

VIH

High-level input voltage

0.7 × VIO

VIO

VIL

Low-level input voltage

0.3 × VIO

IIH

High-level input current

IO = –4 mA, MUTE, SDINA, and SDINB pins

0.5

μA

IO = –4 mA, all other pins

0.5

IIL

Low-level input current

IO = 4 mA

0.5

μA

VOH

High-level output voltage

0.8 × VIO

VIO

VOL

Low-level output voltage

0.2 × VIO

CIN

Input capacitance

LINE RECEIVER INPUTS (RX1+, RX1–, RX2+, RX2–, RX3+, RX3–, RX4+, RX4–)

VTH

Differential input sensitivity

Voltage across a given differential input pair

150

200

VHY

Input hysteresis

150

LINE DRIVER OUTPUTS (TX+, TX–)

VTXO

Differential output voltage

RL = 110 Ω across TX+ and TX–

5.4

VPP

MASTER CLOCK INPUT

fMCLK

Master clock input (MCLK) frequency

27.7

MHz

fMCLKD

Master clock input (MCLK) duty cycle

45%

55%

DIGITAL AUDIO INTERFACE RECEIVER (DIR)

DIX4192 Datasheet(PDF) 6 Page - Texas Instruments

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