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LM3697 Datasheet(PDF) 7 Page - Texas Instruments |
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LM3697 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 42 page ![]() t4 t2 t3 t5 t1 SCL SDA_IN SDA_OUT 7 LM3697 www.ti.com SNOSCS2D – NOVEMBER 2013 – REVISED MARCH 2019 Product Folder Links: LM3697 Submit Documentation Feedback Copyright © 2013–2019, Texas Instruments Incorporated Electrical Characteristics (continued) Limits apply over the full operating ambient temperature range ( −40°C ≤ TA ≤ 85°C) and VIN = 3.6 V, unless otherwise specified. (1)(2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PWM INPUT VPWM_L Input logic low 2.7 V ≤ VIN ≤ 5.5 V 0 0.4 V VPWM_H Input logic high 2.7V ≤ VIN ≤ 5.5 V 1.31 VIN tPWM Minimum PWM input pulse 2.7 V ≤ VIN ≤ 5.5 V, PWM zero detect enabled 0.75 µs I2C-COMPATIBLE VOLTAGE SPECIFICATIONS (SCL, SDA) VIL Input logic low 2.7 V ≤ VIN ≤ 5.5 V 0 0.4 V VIH Input logic high 2.7 V ≤ VIN ≤ 5.5 V 1.29 VIN VOL Output logic low (SDA) 2.7 V ≤ VIN ≤ 5.5 V, ILOAD = 3 mA 400 mV (1) SCL and SDA must be glitch-free in order for proper brightness control to be realized. 6.6 Timing Requirements MIN NOM MAX UNIT I2C-COMPATIBLE TIMING SPECIFICATIONS (SCL, SDA)(1) t1 SCL (clock period) 2.7 V ≤ VIN ≤ 5.5 V 2.5 µs t2 Data In set-up time to SCL high 2.7 V ≤ VIN ≤ 5.5 V 100 ns t3 Data out stable after SCL low 2.7 V ≤ VIN ≤ 5.5 V 0 ns t4 SDA low set-up time to SCL low (start) 2.7 V ≤ VIN ≤ 5.5 V 100 ns t5 SDA high hold time after SCL high (stop) 2.7 V ≤ VIN ≤ 5.5 V 100 ns INTERNAL POR THRESHOLD AND HWEN TIMING SPECIFICATION VPOR POR reset release voltage threshold VIN ramp time = 100 µs 1.7 2.1 V VIN ramp time = 100 µs, TA = 25°C 1.9 tHWEN First I2C start pulse after HWEN high 2.7 V ≤ VIN ≤ 5.5 V, POR reset complete 20 µs POR reset complete, TA = 25°C 5.0 Figure 1. I2C-Compatible Interface Timing |
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