AM486DE2 datasheet(29/52 Pages) AMD

29 / 52 page

Am486DE2 Microprocessor

This is necessary because the SMI handler operates

from a distinct address space (SMRAM) and the debug

trap does not represent the normal system memory

space.

For an SMI handler to use the debug trap feature of the

processor to debug SMI handler code, it must first en-

sure that an SMM-compliant debug handler is available.

The SMI handler must also ensure DR3–DR0 is saved

to be restored later. The debug registers DR3–DR0 and

DR7 must then be initialized with the appropriate values.

For the processor to use the single-step feature of the

processor, it must ensure that an SMM-compliant sin-

gle-step handler is available and then set the trap flag

in the EFLAGS register. If the system design requires

the processor to respond to hardware INTR requests

while in SMM, it must ensure that an SMM-compliant

interrupt handler is available, and then set the interrupt

flag in the EFLAGS register (using the STI instruction).

Software interrupts are not blocked on entry to SMM,

and the system software designer must provide an

SMM-compliant interrupt handler before attempting to

execute any software interrupt instructions. Note that in

SMM mode the interrupt vector table has the same prop-

erties and location as the Real mode vector table.

NMI interrupts are blocked on entry to the SMI handler.

If an NMI request occurs during the SMI handler, it is

latched and serviced after the processor exits SMM.

Only one NMI request is latched during the SMI handler.

If an NMI request is pending when the processor exe-

cutes the RSM instruction, the NMI is serviced before

the next instruction of the interrupted code sequence.

Although NMI requests are blocked when the CPU en-

ters SMM, they may be enabled through software by

executing an IRET instruction. If the SMI handler re-

quires the use of NMI interrupts, it should invoke a dum-

my interrupt service routine to execute an IRET

instruction. When an IRET instruction is executed, NMI

interrupt requests are serviced in the same Real mode

manner in which they are handled outside of SMM.

SMM Revisions Identifier

The 32-bit SMM Revision Identifier specifies the version

of SMM and the extensions that are available on the

processor. The fields of the SMM Revision Identifiers

and bit definitions are shown in Table 6 and Table 7. Bit

17 or 16 indicates whether the feature is supported

(1=supported, 0=not supported). The processor always

reads the SMM Revision Identifier at the time of a re-

store. The I/O Trap Extension and SMM Base Reloca-

tion bits are fixed. The processor writes these bits out

at the time it performs a save state.

Note: Changing the state of the reserved bits may result

in unpredictable processor behavior.

Table 6. System Management Mode Revision Identifier

31–18

15–0

Reserved

SMM Base

Relocation

I/O Trap

Extension

SMM Revision Level

00000000000000

0000h

Table 7. SMM Revision Identifier Bit Definitions

Bit Name

Description

Default

State

State at SMM

Entry

State at

SMM Exit

Notes

SMM Base

Relocation

1=SMM Base Relocation Available

0=SMM Base Relocation

Unavailable

No Change in State

I/O Trap Extension

1=I/O Trapping Available

0=I/O Trapping Unavailable

No Change in State

AM486DE2 Datasheet(PDF) 29 Page - Advanced Micro Devices

AM486DE2 Datasheet(HTML) 29 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL