AM486DE2 datasheet(36/52 Pages) AMD

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Am486DE2 Microprocessor

TEST REGISTERS 4 AND 5 MODIFICATIONS

The Cache Test Registers for the Am486DE2 micropro-

cessor are the same test registers (TR3, TR4, and TR5)

provided in earlier Am486DX and DX2 microprocessors.

TR3 is the cache test data register. TR4, the cache test

status register, and TR5, the cache test control register,

operate together with TR3.

When WB/WT meets the necessary setup timing and is

sampled Low on the falling edge of RESET, the proces-

sor is placed in Write-through mode and the test register

function is identical to the earlier Am486 microproces-

sors. Table 10 and Table 11 show the individual bit func-

tions of these registers. “TR4 Definition” on page 36 and

“TR5 Definition” on page 36 provide a detailed descrip-

tion of the field functions.

TR4 Definition

This section includes a detailed description of the bit

fields defined for TR4.

Note: Bits listed in Table 10 as Not used are not included

in these descriptions.

s Tag (bits 31–11): Read/Write, always available in

Write-through mode. For a cache write, this is the tag

that specifies the address in memory. On a cache look-

up, this is the tag for the selected entry in the cache.

s Valid (bit 10): Read/Write. This is the Valid bit for the

accessed entry. On a cache look-up, Valid is a copy

of one of the bits reported in bits 6–3. On a cache-

write in Write-through mode, Valid becomes the new

valid bit for the selected entry and set.

s LRU (bits 9–7): Read Only, independent of the Ext

bit in TR5. On a cache look-up, these are the three

LRU bits of the accessed set. On a cache write,

these bits are ignored; the LRU bits in the cache are

updated by the pseudo-LRU cache replacement

algorithm. Write operations to these locations have

no effect on the device.

s Valid (bits 6–3): Read Only. On a cache look-up,

these are the four Valid bits of the accessed set.

Write operations to these locations have no effect on

the device.

TR5 Definition

This section includes a detailed description of the bit

fields in TR5.

Note: Bits listed in Table 11 as Not used are not included

in the descriptions.

s Index (bits 10–4): Read/Write. Index selects one of

the 128 sets.

s Entry (bits 3–2): Read/Write. Entry selects between

one of the four entries in the set addressed by the

Set Select during a cache read or write.

During

cache-fill buffer writes or cache-read buffer reads,

the value in the Entry field selects one of the four

doublewords in a cache line.

s Control (bits 1–0): Read/Write. The control bits

determine which operation is to be performed. The

following is a definition of the control operations:

— 00 = Write to cache fill buffer, or read from cache

read buffer.

— 01 = Perform cache write.

— 10 = Perform cache read.

— 11 = Flush the cache (mark all entries invalid)

Table 10. Test Register (TR4)

30–29

27–26

25–24

23–22

21–20

15–

9–7

6–3

2–0

EXT = 0

Tag

Valid

LRU

Valid

(rd)

Not

used

Table 11. Test Register (TR5)

31–20

18–17

15–11

10–4

3–2

1–0

Write-Through

Not used

Index

Entry

Control

AM486DE2 Datasheet(PDF) 36 Page - Advanced Micro Devices

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