AM486DE2 datasheet(14/52 Pages) AMD

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Am486DE2 Microprocessor

This signal is used in cache snooping. The Am486DE2

processor does not support write-back cache. EADS

has a weak internal pull-up, which disables this pin.

FERR

Floating-Point Error (Active-Low Output)

Driven active when a floating-point error occurs, FERR

is similar to the ERROR pin on a 387 math coprocessor.

FERR is included for compatibility with systems using

DOS-type floating-point error reporting. FERR is active

Low and is not floated during bus hold, except during

Three-state Test mode (see FLUSH).

FLUSH (Modified)

Cache Flush (Active-Low Input)

In Write-through mode, FLUSH invalidates the cache

without issuing a special bus cycle. FLUSH is an active

Low input that needs to be asserted only for one clock.

FLUSH is asynchronous, but setup and hold times t20

and t21 must be met for recognition in any specific clock.

Sampling FLUSH Low in the clock before the falling

edge of RESET causes the microprocessor to enter

Three-state Test mode.

HITM (New)

Hit Modified Line (Active-Low Output)

In Write-through mode, HITM floats at all times.

HLDA

Hold Acknowledge (Output)

The HLDA signal is activated in response to a hold re-

quest presented on the HOLD pin. HLDA indicates that

the microprocessor has given the bus to another local

bus master. HLDA is driven active in the same clock in

which the microprocessor floats its bus. HLDA is driven

inactive when leaving bus hold. HLDA is active High and

remains driven during bus hold. HLDA is floated only

during Three-state Test mode. (See FLUSH.)

HOLD

Bus Hold Request (Input)

HOLD gives control of the microprocessor bus to anoth-

er bus master. In response to HOLD going active, the

microprocessor floats most of its output and input/output

pins. HLDA is asserted after completing the current bus

cycle, burst cycle, or sequence of locked cycles. The

microprocessor remains in this state until HOLD is deas-

serted. HOLD is active High and does not have an in-

ternal pull-down resistor. HOLD must satisfy setup and

hold times t18 and t19 for proper operation.

IGNNE

Ignore Numeric Error (Active-Low Input)

When this pin is asserted, the Am486DE2 microproces-

sor will ignore a numeric error and continue executing

non-control floating-point instructions. When IGNNE is

deasserted, the Am486DE2 microprocessor will freeze

on a non-control floating-point instruction if a previous

floating-point instruction caused an error. IGNNE has

no effect when the NE bit in Control Register 0 is set.

IGNNE is active Low and is provided with a small internal

pull-up resistor. IGNNE is asynchronous but must meet

setup and hold times t20 and t21 to ensure recognition in

any specific clock.

INTR

Maskable Interrupt (Input)

When asserted, this signal indicates that an external

interrupt has been generated. If the internal interrupt flag

is set in EFLAGS, active interrupt processing is initiated.

The microprocessor generates two locked interrupt ac-

knowledge bus cycles in response to the INTR pin going

active. INTR must remain active until the interrupt ac-

knowledges have been performed to ensure that the

interrupt is recognized. INTR is active High and is not

provided with an internal pull-down resistor. INTR is

asynchronous, but must meet setup and hold times t20

and t

21 for recognition in any specific clock.

INV (New)

Invalidate (Input)

The external system asserts INV to invalidate the cache-

line state when an external bus master proposes a write.

It is sampled together with A31–A4 during the clock in

which EADS is active. INV has an internal weak pull-up.

INV is ignored in Write-through mode.

KEN

Cache Enable (Active-Low Input)

KEN determines whether the current cycle is cacheable.

When the microprocessor generates a cacheable cycle

and KEN is active one clock before RDY or BRDY during

the first transfer of the cycle, the cycle becomes a cache-

line-fill cycle. Returning KEN active one clock before

RDY during the last read in the cache line fill causes the

line to be placed in the on-chip cache. KEN is active Low

and is provided with a small internal pull-up resistor.

KEN must satisfy setup and hold times t

14 and t15 for

proper operation.

LOCK

Bus Lock (Active-Low Output)

A Low output on this pin indicates that the current bus

cycle is locked. The microprocessor ignores HOLD

when LOCK is asserted (although it does acknowledge

AHOLD and BOFF). LOCK goes active in the first clock

of the first locked bus cycle and goes inactive after the

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