AM486DE2 datasheet(32/52 Pages) AMD

32 / 52 page

Am486DE2 Microprocessor

s To implement a 0-V suspend function, the system

must have access to all normal system memory from

within an SMI handler routine. If the SMRAM

overlays normal system memory (see Figure 14),

there must be a method to access overlaid system

memory independently.

The recommended configuration is to use a separate

(nonoverlaid) physical address for SMRAM. This non-

overlaid scheme prevents the CPU from improperly ac-

cessing the SMRAM or system RAM directly or through

the cache. Figure 15 shows the relative SMM timing for

nonoverlaid SMRAM for systems configured in Write-

through mode.

When the default SMRAM location is used, however,

SMRAM is overlaid with system main memory (at

38000h–3FFFFh). For simplicity, system designers may

want to use this default address, or they may select

another overlaid address range. However, in this case

the system control circuitry must use SMIACT to distin-

guish between SMRAM and main system memory, and

must restrict SMRAM space access to the CPU only. To

maintain cache coherency and to ensure proper system

operation in systems configured in Write-through mode,

the system must flush both the CPU internal cache and

any second-level caches in response to SMIACT going

Low. A system that uses cache during SMM must flush

the cache a second time in response to SMIACT going

High (see Figure 16). If KEN is driven High when FLUSH

is asserted, the cache is disabled and a second flush is

not required (see Figure 17).

Cache Flushes

The CPU does not unconditionally flush its cache before

entering SMM. Therefore, the designer must ensure

that, for systems using overlaid SMRAM, the cache is

flushed upon SMM entry, and SMM exit if caching is

enabled.

If the flush at SMM entry is not done, the first SMM read

could hit in a cache that contains normal memory space

code/data instead of the required SMI handler and the

handler could not be executed. If the cache is not dis-

abled and cache is not flushed at SMM exit, the normal

read cycles after SMM may hit in a cache that may con-

tain SMM code/data instead of the normal system mem-

ory contents.

In Write-through mode, assert the FLUSH signal in re-

sponse to the assertion of SMIACT at SMM entry, and

if required because the cache is enabled, assert FLUSH

again in response to the deassertion of SMIACT at SMM

exit (see Figure 16 and Figure 17).

Reloading the state registers at the end of SMM restores

cache functionality to its pre-SMM state.

Figure 14. SMRAM Location

Non-overlaid

(no need to flush

caches)

Overlaid

(caches must

be flushed)

Normal

memory

Normal

memory

SMRAM

Normal

memory

Overlaid region

SMRAM

Figure 15. SMM Timing in Systems Using Non-Overlaid Memory Space and Write-Through Mode with

Caching Enabled During SMM

State

Save

SMI Handler

State Resume

Normal

Cycle

RSM

SMI

SMIACT

AM486DE2 Datasheet(PDF) 32 Page - Advanced Micro Devices

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