AM486DE2 datasheet(33/52 Pages) AMD

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Am486DE2 Microprocessor

A20M Pin

Systems based on the MS-DOS operating system con-

tain a feature that enables the CPU address bit A20 to

be forced to 0. This limits physical memory to a maxi-

mum of 1 Mbyte, and is provided to ensure compatibility

with those programs that relied on the physical address

wraparound functionality of the original IBM PC. The

A20M pin on Am486DE2 CPUs provides this function.

When A20M is active, all external bus cycles drive A20

Low, and all internal cache accesses are performed with

A20 Low.

The A20M pin is recognized while the CPU is in SMM.

The functionality of the A20M input must be recognized

in two instances:

1. If the SMI handler needs to access system memory

space above 1 Mbyte (for example, when saving

memory to disk for a zero-volt suspend), the A20M

pin must be deasserted before the memory above 1

Mbyte is addressed.

2. If SMRAM has been relocated to address space

above 1 Mbyte and A20M is active upon entering

SMM, the CPU attempts to access SMRAM at the

relocated address, but with A20 Low. This could

cause the system to crash, because there would be

no valid SMM interrupt handler at the accessed

location.

Figure 16. SMM Timing in Systems Using Overlaid Memory Space and Write-Through Mode with Caching

Enabled During SMM

Figure 17. SMM Timing in Systems Using Overlaid Memory Space and Write-Through Mode with Caching

Disabled During SMM

State

Save

SMI Handler

State

Resume

Normal

Cycle

RSM

SMI

SMIACT

FLUSH

SMI

Instruction x

Instruction x+1

Cache contents

invalidated

Cache contents

invalidated

State

Save

SMI Handler

State

Resume

Normal

Cycle

RSM

SMI

SMIACT

FLUSH

SMI

Instruction x

Instruction x+1

Cache contents

invalidated

KEN

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