AM486DE2 datasheet(12/52 Pages) AMD

12 / 52 page

Am486DE2 Microprocessor

PIN DESCRIPTIONS

The Am486DE2 microprocessor is a new member of the

AMD Am486 family, which also includes the Enhanced

Am486 and the Am486DX microprocessors.

Like the AMD Enhanced Am486 family, the Am486DE2

adds new signals to those used by the Am486DX pro-

cessors. These added signals support new processor

features and are indicated as

new in the pin description

titles.

Although the Am486DE2 processor is based on and

compatible with the Enhanced Am486 microprocessors,

it has no support for write-back cache. Because of this,

some Am486DE2 signals are supported differently than

the signals in either the Enhanced Am486 or the

Am486DX microprocessors. These signals are indicat-

ed as

modified in the pin descriptions below.

All other processor signals provide the same function-

ality as the standard Am486DX processor.

A20M

Address Bit 20 Mask (Active-Low Input)

A Low signal on the A20M pin causes the microproces-

sor to mask address line A20 before performing a lookup

to the internal cache, or driving a memory cycle on the

bus. Asserting A20M causes the processor to wrap the

address at 1 Mbyte, emulating Real mode operation.

The signal is asynchronous, but must meet setup and

hold times t20 and t21 for recognition during a specific

clock. During normal operation, A20M should be sam-

pled High at the falling edge of RESET.

A31–A2

Address Lines A31-A4 (Inputs/Outputs)

Address Lines A3-A2 (Outputs)

Pins A31–A2 define a physical area in memory or indi-

cate an input/output (I/O) device. Address lines A31–A4

drive addresses into the microprocessor to perform

cache line invalidations. Input signals must meet setup

and hold times t

22 and t23. A31–A2 are not driven during

bus or address hold.

ADS

Address Status (Active-Low Output)

A Low output from this pin indicates that a valid bus cycle

definition and address are available on the cycle defini-

tion lines and address bus. ADS is driven active by the

same clock as the addresses. ADS is active Low and is not

driven during bus hold.

AHOLD (Modified)

Address Hold (Input)

The external system may assert AHOLD to perform a

cache snoop. In response to the assertion of AHOLD,

the microprocessor stops driving the address bus A31–

A2 in the next clock. The data bus remains active and

data can be transferred for previously issued read or

write bus cycles during address hold. AHOLD is recog-

nized even during RESET and LOCK. The earliest that

AHOLD can be deasserted is two clock cycles after

EADS is asserted to start a cache snoop.

BE3–BE0

Byte Enable (Active-Low Outputs)

The byte enable pins indicate which bytes are enabled

and active during read or write cycles. During the first

cache fill cycle, however, an external system should ig-

nore these signals and assume that all bytes are active.

s BE3 for D31–D24

s BE2 for D23–D16

s BE1 for D15–D8

s BE0 for D7–D0

BE3–BE0 are active Low and are not driven during bus

hold.

BLAST (Modified)

Burst Last (Active-Low Output)

Burst Last goes Low to tell the CPU that the next BRDY

signal completes the burst bus cycle. BLAST is active

for both burst and non-burst cycles. BLAST is active Low

and is not driven during a bus hold.

BOFF

Back Off (Active-Low Input)

This input signal forces the microprocessor to float all

pins normally floated during hold, but HLDA is not as-

serted in response to BOFF. BOFF has higher priority

than RDY or BRDY; if both are returned in the same

clock, BOFF takes effect. The microprocessor remains

in bus hold until BOFF goes High. If a bus cycle is in

progress when BOFF is asserted, the cycle restarts.

BOFF must meet setup and hold times t18 and t19 for

proper operation. BOFF has an internal weak pull-up.

BRDY

Burst Ready Input (Active-Low Input)

The BRDY signal performs the same function during a

burst cycle that RDY performs during a non-burst cycle.

BRDY indicates that the external system has presented

valid data in response to a read, or that the external

system has accepted data in response to write. BRDY

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