TAS3103ADBT datasheet(123/154 Pages) TI2

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4−2

4.3

Electrical Characteristics Over Recommended Operating Conditions (Unless

Otherwise Noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

High-level output

3.3-V LVCMOS

IOH = −4 mA

0.8 VDDS

VOH

High level output

voltage

1.8-V LVCMOS (XTALO)

IOH = −0.55 mA

0.8 AVDD

VOL

Low-level output voltage

3.3-V LVCMOS

IOL = 4 mA

0.22

VDDS

VOL

Low level output voltage

1.8-V LVCMOS (XTALO)

IOL = 0.75 mA

0.22 AVDD

IOZ

High-impedance output

current

3.3-V LVCMOS

±20

μA

Low-level input

3.3-V LVCMOS

VI = VIL

±20

IIL

Low level input

current(1)

1.8-V LVCMOS (XTALI)

VI = VIL

±20

μA

High-level input

3.3-V LVCMOS

VI = VIH

±20

IIH

High level input

current(2)

1.8-V LVCMOS (XTALI)

VI = VIH

±20

μA

DSP clock = 135 MHz,

LRCLK = 96 kHz,

MCLKI/XTALI = 12.228 MHz

DSP clock = 67.5 MHz,

LRCLK = 48 kHz,

MCLKI/XTALI = 12.228 MHz

Digital supply current

DSP clock = 33.75 MHz,

LRCLK = 24 kHz,

MCLKI/XTALI = 12.228 MHz

IDVDD

Digital supply current

LRCLK = 48 kHz,

MCLKI/XTALI = 12.288 MHz,

Power down enabled

3.5

No LRCLK, SCLK.

MCLKI/XTALI = 12.288 MHz,

Power down enabled

2.2

No LRCLK, SCLK, or

MCLKI/XTALI,

Power down enabled

DSP clock = 135 MHz,

LRCLK = 96 kHz,

MCLKI/XTALI = 12.228 MHz

2.9

DSP clock = 67.5 MHz,

LRCLK = 48 kHz,

MCLKI/XTALI = 12.228 MHz

2.7

IA_DVDD

Analog supply current

DSP clock = 33.75 MHz,

LRCLK = 24 kHz,

MCLKI/XTALI = 12.228 MHz

2.4

LRCLK = 48 kHz,

MCLKI/XTALI = 12.288 MHz,

Power down enabled

1.5

No LRCLK, SCLK, or

MCLKI/XTALI,

Power down enabled

1.5

NOTES:

1. Value given is for those input pins that connect to an internal pullup resistor as well as an input buffer. For inputs that have a pulldown

resistor or no resistor, IIL is ±1 μA.

2. Value given is for those input pins that connect to an internal pulldown resistor as well as an input buffer. For inputs that have a pullup

resistor or no resistor, IIH is ±1 μA.

TAS3103ADBT Datasheet(PDF) 123 Page - Texas Instruments

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