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LM5032 Datasheet(PDF) 6 Page - Texas Instruments |
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LM5032 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 36 page ![]() LM5032 SNVS344B – MARCH 2005 – REVISED DECEMBER 2014 www.ti.com Electrical Characteristics (continued) MIN and MAX limits apply –40°C ≤ TJ ≤ 125°C. VIN = 48 V, VCC = 10 V externally applied, RT = RDCL = 42.2kΩ, UVLO = 1.5 V, TJ = 25°C, unless otherwise stated, see (1)and see(2). SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC voltage 2 V Input Sync threshold 2.6 3.3 3.7 V PWM CONTROLLER (COMP1, COMP2, Duty Cycle Limit Pins) Delay to output COMP1 (COMP2) set to 2V. CS1 (CS2) 50 ns stepped from 0 to 0.4V. Time for OUT1 (OUT2) to fall to 90% of VCC. Output load = 0 pF. VCOMP COMP1 (COMP2) open circuit 5 V voltage ICOMP COMP1 (COMP2) short circuit COMP1 (COMP2) = 0V 0.6 1 1.4 mA current COMP1 (COMP2) to PWM1 0.33 V/V (PWM2) gain Minimum duty cycle SS1 (SS2) = 0V 0% Maximum duty cycle 1 UVLO pin = 1.30V, RDCL = RT, COMP1 76% (COMP2) = open Maximum duty cycle 2 UVLO pin = 3.75V, RDCL = RT, COMP1 20% (COMP2) = open Maximum duty cycle 3 UVLO pin = 1.30V, RDCL = RT/4, COMP1 20% (COMP2) = open Maximum duty cycle 4 UVLO pin = 2.50V, RDCL = RT, COMP1 50% (COMP2) = open Maximum duty cycle 5 UVLO pin = 1.30V, RDCL = RT/2, COMP1 40% (COMP2) = open Slope compensation Delta increase at PWM comparator to CS1 90 mV (CS2) Channel mismatch CS1 (CS2) = 0.25V 7% Soft-start to COMP offset SS1 (SS2) = 0.8V 0 V MAIN OUTPUT DRIVERS (OUT1, OUT2) Output high voltage IOUT = 50mA (source) VCC-1 VCC- V 0.2 Output low voltage IOUT = 100 mA (sink) 0.3 1 V Rise time CLOAD = 1 nF 12 ns Fall time CLOAD = 1 nF 10 ns Peak source current 1.5 A Peak sink current 2.5 A THERMAL SHUTDOWN TSD Shutdown temperature 165 °C Hysteresis 20 °C 6 Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: LM5032 |
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