LMX2486 datasheet(28/48 Pages) TI2

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LMX2486

SNAS324B – JANUARY 2006 – REVISED JANUARY 2016

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Table 16. Operation With the 32/33/36/37 Prescaler (RF_P=1) (continued)

RF_N [10:0]

RF_N

RF_C [5:0]

RF_B [2:0]

RF_A [1:0]

...

2039

2040-

Possible with a second or third order delta-sigma engine.

2043

2044-

Possible only with a second order delta-sigma engine.

2045

>2045

N values greater than 2045 are prohibited.

8.6.2 R1 Register

Table 17. R1 Register

DATA[19:0]

RF_P

RF_

RF_R[5:0]

RF_FD[11:0]

8.6.2.1 RF_FD[11:0] -- RF PLL Fractional Denominator

The function of these bits are described in Fractional Denominator Determination { RF_FD[21:12], RF_FD[11:0],

Access[1]}.

8.6.2.2 RF_R [5:0] -- RF R Divider Value

The RF R Counter value is determined by this control word.

NOTE

This counter does allow values down to one.

Table 18. RF R Divider

R VALUE

RF_R[5:0]

...

8.6.2.3 RF_P -- RF Prescaler bit

The prescaler used is determined by this bit.

Table 19. RF PLL Prescaler Select Bit and Frequencies

RF_P

PRESCALER

MAXIMUM FREQUENCY

16/17/20/21

4000 MHz

32/33/36/37

4500 MHz

8.6.2.4 RF_PD -- RF Power Down Control Bit

When this bit is set to 0, the RF PLL operates normally. When it is set to one, the RF PLL is powered down and

the RF Charge pump is set to a TRI-STATE mode. The CE pin and ATPU bit also control power down functions,

and will override the RF_PD bit. The order of precedence is as follows. First, if the CE pin is LOW, then the PLL

will be powered down. Provided this is not the case, the PLL will be powered up if the ATPU bit says to do so,

regardless of the state of the RF_PD bit. After the CE pin and the ATPU bit are considered, then the RF_PD bit

then takes control of the power down function for the RF PLL.

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