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ADV7182ABCPZ Datasheet(PDF) 43 Page - Analog Devices |
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ADV7182ABCPZ Datasheet(HTML) 43 Page - Analog Devices |
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43 / 102 page  Data Sheet ADV7182A Rev. 0 | Page 43 of 102 PHS, HSYNC Polarity—Address 0x37, Bit 7 The polarity of the HSYNC signal can be inverted using the PHS bit. When PHS is 0 (default), HSYNC is active low. When PHS is 1, HSYNC is active high. Table 73. HS Timing Parameters Standard Characteristic HS Begin Adjust, HSB[10:0] (Default) HS End Adjust, HSE[10:0] (Default) HS to Active Video, LLC Clock Cycles, C in Figure 31 (Default) Active Video Samples/ Line, D in Figure 31 Total LLC Clock Cycles, E in Figure 31 NTSC 00000000010b 00000000000b 272 720Y + 720C = 1440 1716 PAL 00000000010b 00000000000b 284 720Y + 720C = 1440 1728 Figure 31. HSYNC Timing E ACTIVE VIDEO LLC PIXEL BUS HS Cr Y FF 00 00 XY 80 10 80 10 80 10 FF 00 00 XY Cb Y Cr Y Cb Y Cr 4 LLC D HSB[10:0] HSE[10:0] C E D SAV ACTIVE VIDEO H BLANK EAV |
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