ADV7182ABCPZ datasheet(10/102 Pages) AD

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ADV7182A

Data Sheet

Rev. 0 | Page 10 of 102

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 4. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Type

Description

1, 4

DGND

Ground

Ground for Digital Supply.

DVDDIO

Power

Digital Input/Output Supply Voltage (1.8 V to 3.3 V).

3, 13

DVDD

Power

Digital Supply Voltage (1.8 V).

5 to 12

P7 to P0

Output

Video Pixel Output Port.

XTALP

Output

Output Pin for the Crystal Oscillator Amplifier. Connect this pin to the external 28.63636 MHz crystal, or

leave it unconnected if an external 1.8 V, 28.63636 MHz clock oscillator source is used to clock the

ADV7182A. The crystal used with the ADV7182A must be a fundamental crystal.

XTALN

Input

Input Pin for the Crystal Oscillator Amplifier. The crystal used with the ADV7182A must be a

fundamental crystal. If an external 1.8 V, 28.63636 MHz clock oscillator source is used to clock the

ADV7182A, the output of the oscillator is fed into the XTALN pin.

PVDD

Power

PLL Supply Voltage (1.8 V).

17, 18,

22, 23

AIN1 to AIN4

Input

Analog Video Input Channels.

VREFP

Output

Positive Internal Voltage Reference Output.

VREFN

Output

Negative Internal Voltage Reference Output.

AVDD

Power

Analog Supply Voltage (1.8 V).

INTRQ

Output

Interrupt Request Output. An interrupt occurs when certain signals are detected on the input video.

RESET

Input

System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to

reset the ADV7182A circuitry.

ALSB

Input

Address Least Significant Bit. This pin selects the I2C address for the ADV7182A. For ALSB set to Logic 0,

the address selected for a write is 0x40; for ALSB set to Logic 1, the address selected is 0x42.

SDATA

Input/

output

I2C Port Serial Data Input/Output Pin.

SCLK

Input

I2C Port Serial Clock Input. The maximum clock rate is 400 kHz.

VS/FIELD/SFL

Output

Vertical Synchronization Output Signal (VS)/Field Synchronization Output Signal (FIELD)/

Subcarrier Frequency Lock (SFL). This pin contains a serial output stream that can be used to lock the

subcarrier frequency when this decoder is connected to any Analog Devices, Inc., digital video encoder.

Output

Horizontal Synchronization Output Signal.

PWRDWN

Input

Power-Down. A logic low on this pin places the ADV7182A in power-down mode.

LLC

Output

Line Locked Clock for Output Pixel Data. This pin is nominally 27 MHz but varies up or down according

to the video line length.

EPAD (EP)

Exposed Ground Pad. The exposed pad must be connected, together with the DGND pins, to a

common ground plane (GND).

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED,

TOGETHER WITH THE DGND PINS, TO A

COMMON GROUND PLANE (GND).

24 INTRQ

23 AIN4

22 AIN3

21 AVDD

20 VREFN

19 VREFP

18 AIN2

17 AIN1

DGND

DVDDIO

DVDD

DGND

ADV7182A

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