ADV7182ABCPZ datasheet(18/102 Pages) AD

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ADV7182A

Data Sheet

Rev. 0 | Page 18 of 102

GLOBAL CONTROL REGISTERS

POWER SAVING MODES

Power-Down

PWRDWN—Address 0x0F, Bit 5

The ADV7182A can be placed into a chip wide, power-down mode

by setting the PWRDWN bit or by using the PWRDWN pin. The

power-down mode stops the clock from entering the digital

section of the chip, thereby freezing its operation. No I2C bits are

lost during power-down mode. The PWRDWN bit also affects

the analog blocks and switches them into low current modes.

The I2C interface is unaffected and remains operational in

power-down mode.

When PWRDWN is 0, the chip is operational. When PWRDWN is

1 (default), the ADV7182A is in a chip-wide, power-down mode.

RESET CONTROL

Reset, Chip Reset—Address 0x0F, Bit 7

Setting this bit, which is equivalent to controlling the RESET pin on

the ADV7182A, issues a full chip reset. All I2C registers are reset

to their default/power-up values. Note that some register bits do

not have a reset value specified and keep the last written value.

These bits are marked as having a reset value of x in the register

tables (see Table 96 and Table 98). After the reset sequence, the

device immediately starts to acquire the incoming video signal.

After setting the reset bit (or initiating a reset via the RESET pin),

the device returns to the default for its primary mode of operation.

All I2C bits are loaded with their default values, making this bit

self clearing. Executing a software reset takes approximately 2 ms.

However, it is recommended to wait 5 ms before any further I2C

writes are performed.

The I2C master controller receives a no acknowledge condition

on the ninth clock cycle when chip reset is implemented (see

the I2C Interface section).

When the reset bit is 0 (default), operation is normal. When the

reset bit is 1, the reset sequence starts.

GLOBAL PIN CONTROL

Tristate Output Drivers

TOD—Address 0x03, Bit 6

This bit allows the user to tristate the output drivers of the

ADV7182A.

Upon setting the TOD bit, the P7 to P0, HS, and VS/FIELD/

SFL pins are tristated.

The timing pins (HS and VS/FIELD/SFL) can be forced active

via the TIM_OE bit. For more information on tristate control,

see the Tristate LLC Driver section and the Timing Signals

Output Enable section.

Individual drive strength controls are provided via the

DR_STR_x bits.

When TOD is 0, the output drivers are enabled. When TOD is 1

(default), the output drivers are tristated.

Tristate LLC Driver

TRI_LLC—Address 0x1D, Bit 7

This bit allows the output drivers for the LLC pin of the

ADV7182A to be tristated. For more information on tristate

control, refer to the Tristate Output Drivers section and the

Timing Signals Output Enable section.

Individual drive strength controls are provided via the

DR_STR_x bits.

When TRI_LLC is 0, the LLC pin drivers work according to the

DR_STR_C[1:0] setting (pin enabled). When TRI_LLC is 1

(default), the LLC pin drivers are tristated.

Timing Signals Output Enable

TIM_OE—Address 0x04, Bit 3

Regard the TIM_OE bit as an addition to the TOD bit. Setting

this bit high forces the output drivers for HS and VS/FIELD/SFL

into the active state (that is, driving state), even if the TOD bit is

set. If TIM_OE is set to low, the HS and VS/FIELD/SFL pins

are tristated depending on the TOD bit. This functionality is

beneficial if the decoder is used only as a timing generator,

which may be the case if only the timing signals are extracted

from an incoming signal or if the device is in freerun mode,

where a separate chip can output a company logo, for example.

For more information on tristate control, see the Tristate

Output Drivers section and the Tristate LLC Driver section.

Individual drive strength controls are provided via the

DR_STR_x bits.

When TIM_OE is 0 (default), HS and VS/FIELD/SFL are

tristated according to the TOD bit. When TIM_OE is 1, HS and

VS/FIELD/SFL are always forced active.

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