ADC3663 datasheet(59/92 Pages) TI2

59 / 92 page

Figure 8-60. Register 0x11

SE A

SE B

DLL PDN

AZ EN

R/W-0

Table 8-20. Register 0x11 Field Descriptions

Bit

Field

Type

Reset

Description

7-6

R/W

Must write 0

SE A

R/W

This bit enables single ended analog input, channel A. In this

mode the SNR reduces by 3-dB.

0: Differential input

1: Single ended input

SE B

R/W

This bit enables single ended analog input, channel B. In this

mode the SNR reduces by 3-dB.

0: Differential input

1: Single ended input

R/W

Must write 0

DLL PDN

R/W

This register applies ONLY to the ADC3663. It powers down the

internal DLL, which is used to adjust the sampling time. This

below 40 MSPS. When DLL PDN bit is enabled the sampling

time is directly dependent on sampling clock duty cycle (with a

50/50 duty the sampling time is TS/2).

0: Sampling time is TS/ 4

1: Sampling time is TS/2 (only for sampling rates below 40

MSPS).

R/W

Must write 0

AZ EN

R/W

0/1

This bit enables the internal auto-zero circuitry. It is enabled by

default for the ADC3661/62 and disabled for the ADC3663.

ADC3661/62:

0: Auto-zero enabled

1: Auto-zero disabled

ADC3663:

0: Auto-zero disabled

1: Auto-zero enabled

www.ti.com

ADC3661, ADC3662, ADC3663

SBAS991B – FEBRUARY 2021 – REVISED SEPTEMBER 2022

Submit Document Feedback

Product Folder Links: ADC3661 ADC3662 ADC3663

ADC3663 Datasheet(PDF) 59 Page - Texas Instruments

ADC3663 Datasheet(HTML) 59 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

Datasheet Download

Link URL