Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

ADC3663 Datasheet(PDF) 64 Page - Texas Instruments

Part # ADC3663
Description  ADC366x 16-Bit, 0.5-MSPS to 65-MSPS, Low-Noise, Low Power, Dual-Channel ADC
PDF  92 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

ADC3663 Datasheet(HTML) 64 Page - Texas Instruments

Back Button ADC3663 Datasheet HTML 60Page - Texas Instruments ADC3663 Datasheet HTML 61Page - Texas Instruments ADC3663 Datasheet HTML 62Page - Texas Instruments ADC3663 Datasheet HTML 63Page - Texas Instruments ADC3663 Datasheet HTML 64Page - Texas Instruments ADC3663 Datasheet HTML 65Page - Texas Instruments ADC3663 Datasheet HTML 66Page - Texas Instruments ADC3663 Datasheet HTML 67Page - Texas Instruments ADC3663 Datasheet HTML 68Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 64 / 92 page
background image
Figure 8-68. Register 0x24
7
6
5
4
3
2
1
0
0
0
CH AVG EN
DDC MUX
DIG BYP
DDC EN
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 8-31. Register 0x24 Field Descriptions
Bit
Field
Type
Reset
Description
7-6
0
R/W
0
Must write 0
5
CH AVG EN
R/W
0
Averages the output of ADC channel A and channel B together.
The DDC MUX has to be enabled and set to '11'. The
decimation filter needs to be enabled and set to bypass (fullrate
output) or decimation and DIG BYP set to 1.
0: Channel averaging feature disabled
1: Output of channel A and channel B are averaged: (A+B)/2.
4-3
DDC MUX
R/W
0
Configures DDC MUX in front of the decimation filter.
00: ADC channel A connected to DDC A; ADC Channel B
connected to DDC B
01: ADC channel A connected to DDC A and DDC B.
10: ADC channel B connected to DDC A and DDC B.
11: Output of ADC averaging block (see CH AVG EN) given to
DDC A and DDC B.
2
DIG BYP
R/W
0
This bit needs to be set to enable digital features block which
includes decimation and scrambling.
0: Digital feature block bypassed - lowest latency
1: Data path includes digital features
1
DDC EN
R/W
0
Enables internal decimation filter for both channels
0: DDC disabled.
1: DDC enabled.
0
0
R/W
0
Must write 0
N
DDC MUX
DECIMATION
DDC
DIG BYP
To output
interface
N
DDC
To output
interface
CH
Average
Figure 8-69. Register control for digital features
ADC3661, ADC3662, ADC3663
SBAS991B – FEBRUARY 2021 – REVISED SEPTEMBER 2022
www.ti.com
64
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: ADC3661 ADC3662 ADC3663



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com