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ADC3663 Datasheet(PDF) 76 Page - Texas Instruments |
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ADC3663 Datasheet(HTML) 76 Page - Texas Instruments |
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76 / 92 page  9.4.2 Layout Example The following screen shot shows the top layer of the ADC366x/368x EVM. • Signal and clock inputs are routed as differential signals on the top layer avoiding vias. • SLVDS output interface lanes are routed differential and length matched • Bypass caps are close to the VREF pin on the top layer avoiding vias. SLVDS routed tightly coupled and length matched Bypass caps on VREF close to the pins and no vias Analog inputs on top layer (no vias) Clock routing without vias Figure 9-10. Layout example: top layer of ADC366x/368x EVM ADC3661, ADC3662, ADC3663 SBAS991B – FEBRUARY 2021 – REVISED SEPTEMBER 2022 www.ti.com 76 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ADC3661 ADC3662 ADC3663 |
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