ADS54J20 datasheet(2/117 Pages) TI2

2 / 117 page

Table of Contents

1 Features............................................................................1

2 Applications..................................................................... 1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 ADS54J40 Comparison................................................... 5

6 Pin Configuration and Functions...................................5

7 Specifications.................................................................. 8

7.1 Absolute Maximum Ratings........................................ 8

7.2 ESD Ratings............................................................... 8

7.3 Recommended Operating Conditions.........................9

7.4 Thermal Information....................................................9

7.5 Electrical Characteristics...........................................10

7.6 AC Characteristics.................................................... 11

7.7 Digital Characteristics............................................... 14

7.8 Timing Requirements................................................15

7.9 Typical Characteristics.............................................. 17

8 Detailed Description......................................................27

8.1 Overview................................................................... 27

8.2 Functional Block Diagram......................................... 27

8.3 Feature Description...................................................28

8.4 Device Functional Modes..........................................36

8.5 Register Maps...........................................................48

9 Application Information Disclaimer............................. 85

9.1 Application Information............................................. 85

9.2 Typical Application.................................................. 103

10 Power Supply Recommendations............................106

10.1 Power Sequencing and Initialization..................... 106

11 Layout......................................................................... 107

11.1 Layout Guidelines................................................. 107

11.2 Layout Example.................................................... 107

12 Device and Documentation Support........................108

12.1 Documentation Support........................................ 108

12.2 Receiving Notification of Documentation Updates108

12.3 Support Resources............................................... 108

12.4 Trademarks...........................................................108

12.5 Electrostatic Discharge Caution............................108

12.6 Glossary................................................................108

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (January 2017) to Revision C (December 2020)

Page

• Added text '(Including Interleaving Tones)' to Features bullet............................................................................ 1

• Added ADS54J40 Comparison section, moved Device Comparison Table to this section.................................5

• Changed the description of SYSREFM, SYSREFP, and PDN pins in Pin Functions table ............................... 5

• Changed fIN = 470 MHz test conditions and typical values across parameters in AC Characteristics table.... 11

• Added fIN = 720 MHz test conditions across parameters in AC Characteristics table...................................... 11

• Changed ENOB unit from dBFS to Bits in AC Characteristics table.................................................................11

• Changed typical values of SFDR_IL parameter ...............................................................................................11

• Changed first IMD3 typical value from –85 dBFS to –89 dBFS ....................................................................... 11

• Changed first footnote in Timing Characteristics table..................................................................................... 15

• Changed typical value of FOVR latency from 18 + 4 ns to 18 .........................................................................15

• Changed tPD parameter name to tPDI in Timing Characteristics table.............................................................. 15

• Changed FFT for 470-MHz Input Signal at –3 dBFS figure, title, and conditions............................................. 17

• Added FFT for 720-MHz Input Signal at –6 dBFS figure.................................................................................. 17

• Changed Spurious-Free Dynamic Range vs Input Frequency figure............................................................... 17

• Changed IL Spur vs Input Frequency figure..................................................................................................... 17

• Changed 16-bit to 14-bit in first sentence of Overview section.........................................................................27

• Added DDC Block section ............................................................................................................................... 30

• Changed Table 8-6 .......................................................................................................................................... 36

• Added last sentence to Step 4 in Serial Register Readout: Analog Bank section............................................ 39

• Added last sentence to Step 4 in Serial Register Readout: JESD Bank section.............................................. 40

• Added SDOUT Timing Diagram figure............................................................................................................. 40

• Changed the JESD204B Test Patterns section ............................................................................................... 43

• Changed Serial Interface Registers diagram....................................................................................................48

• Added register addresses 1 and 2 to GENERAL REGISTERS in Register Map section ................................ 48

• Changed the name of JESD ANALOG PAGE (6A00h) to JESD ANALOG PAGE (JESD BANK PAGE

SEL=6A00h) in Register Map table ................................................................................................................. 48

ADS54J40

SBAS714C – MAY 2015 – REVISED DECEMBER 2020

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