ADS54J20 datasheet(6/117 Pages) TI2

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Table 6-1. Pin Functions

I/O

DESCRIPTION

NAME

NO.

CLOCK, SYSREF

CLKINM

Negative differential clock input for the ADC.

CLKINP

Positive differential clock input for the ADC.

SYSREFM

Negative external SYSREF input. Connect this pin to GND if not used.

SYSREFP

Positive external SYSREF input. Connect this pin to 1.8 V if not used.

CONTROL, SERIAL

PDN

I/O

Power down, active low pin. Can be configured via an SPI register setting.

Can be configured to fast overrange output for channel A through the SPI. This pin

has an internal 20kΩ pulldown resistor.

RESET

Hardware reset; active high. This pin has an internal 20-kΩ pulldown resistor.

SCLK

Serial interface clock input

SDIN

Serial interface data input

SDOUT

Serial interface data output.

Can be configured to fast overrange output for channel B through the SPI.

SEN

Serial interface enable

DATA INTERFACE

DA0M

JESD204B serial data negative outputs for channel A

DA1M

DA2M

DA3M

DA0P

JESD204B serial data positive outputs for channel A

DA1P

DA2P

DA3P

DB0M

JESD204B serial data negative outputs for channel B

DB1M

DB2M

DB3M

DB0P

JESD204B serial data positive outputs for channel B

DB1P

DB2P

DB3P

SYNC

Synchronization input for the JESD204B port

INPUT, COMMON MODE

INAM

Differential analog negative input for channel A

INAP

Differential analog positive input for channel A

INBM

Differential analog negative input for channel B

INBP

Differential analog positive input for channel B

VCM

Common-mode voltage, 2.1 V.

Note that analog inputs are internally biased to this pin through 600 Ω (effective), no

external connection from the VCM pin to the INxP or INxM pin is required.

POWER SUPPLY

AGND

18, 23, 26, 29, 32, 36, 37

Analog ground

AVDD

9, 12, 15, 17, 25, 30, 35, 38,

40, 43, 44, 46

Analog 1.9-V power supply

AVDD3V

10, 16, 24, 31, 39, 45

Analog 3.0-V power supply for the analog buffer

ADS54J40

SBAS714C – MAY 2015 – REVISED DECEMBER 2020

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