ADS54J20 datasheet(43/117 Pages) TI2

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8.4.3.1 JESD204B Initial Lane Alignment (ILA)

The initial lane alignment process is started when the receiving device de-asserts the SYNC signal, as shown in

Figure 8-21. When a logic low is detected on the SYNC input pin, the ADS54J40 starts transmitting comma

(K28.5) characters to establish a code group synchronization.

When synchronization is complete, the receiving device asserts the SYNC signal and the ADS54J40 starts the

initial lane alignment sequence with the next local multi-frame clock boundary. The ADS54J40 transmits four

multi-frames, each containing K frames (K is SPI programmable). Each of the multi-frames contains the frame

start and end symbols and the second multi-frame also contains the JESD204 link configuration data.

SYNC

SYSREF

LMFC Clock

LMFC Boundary

xxx

Transmit Data

K28.5

ILA

DATA

Multi

Frame

Code Group

Synchronization

Initial Lane

Alignment

Data Transmission

Figure 8-21. Lane Alignment Sequence

8.4.3.2 JESD204B Test Patterns

There are three different test patterns available in the transport layer of the JESD204B interface. The ADS54J40

supports a clock output-encoded test pattern, and a 12-octet RPAT. These test patterns can be enabled via an

SPI register write and are located in the JESD digital page of the JESD bank.

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ADS54J40

SBAS714C – MAY 2015 – REVISED DECEMBER 2020

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ADS54J20 Datasheet(PDF) 43 Page - Texas Instruments