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ADS54J20 Datasheet(PDF) 46 Page - Texas Instruments |
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ADS54J20 Datasheet(HTML) 46 Page - Texas Instruments |
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46 / 117 page  Table 8-14. Program Summary of DDC Modes and JESD Link Configuration LMFS OPTIONS DDC MODES PROGRAMMING JESD LINK (LMFS) PROGRAMMING L M F S DECIMATI ON OPTIONS DEC MODE EN, DECFIL EN(1) DECFIL MODE[3:0](2) JESD FILTER(3) JESD MODE(4) JESD PLL MODE(5) LANE SHARE(6) DA_BUS_ REORDER (7) DB_BUS_ REORDER (8) BUS_REO RDER EN1(9) BUS_REO RDER EN2(10) 4 2 1 1 No decimation 00 00 000 100 10 0 00h 00h 0 0 4 2 4 4 No decimation 00 00 000 010 10 0 00h 00h 0 0 8 2 2 4 No decimation (default after reset) 00 00 000 001 00 0 00h 00h 0 0 4 4 2 1 4X (IQ) 11 0011 (LPF with fS / 4 mixer) 111 001 00 0 0Ah 0Ah 1 1 4 2 2 2 2X 11 0010 (LPF) or 0110 (HPF) 110 001 00 0 0Ah 0Ah 1 1 2 2 4 2 2X 11 0010 (LPF) or 0110 (HPF) 110 010 10 0 0Ah 0Ah 1 1 2 2 2 1 4X 11 0000, 0100, 1000, or 1100 (all BPFs with different center frequencies). 100 001 00 0 0Ah 0Ah 1 1 2 4 4 1 4X (IQ) 11 0011 (LPF with an fS / 4 mixer) 111 010 10 0 0Ah 0Ah 1 1 1 2 4 1 4X 11 0000, 0100, 1000, or 1100 (all BPFs with different center frequencies) 100 010 10 1 0Ah 0Ah 1 1 (1) The DEC MODE EN and DECFIL EN register bits are located in the main digital page, register 04Dh (bit 3) and register 041h (bit 4). (2) The DECFIL MODE[3:0] register bits are located in the main digital page, register 041h (bits 5 and 2-0). (3) The JESD FILTER register bits are located in the JESD digital page, register 001h (bits 5-3). (4) The JESD MODE register bits are located in the JESD digital page, register 001h (bits 2:0). (5) The JESD PLL MODE register bits are located in the JESD analog page, register 016h (bits 1-0). (6) The LANE SHARE register bit is located in the JESD digital page, register 016h (bit 4). (7) The DA_BUS_REORDER register bits are located in the JESD digital page, register 031h (bits 7-0). (8) The DB_BUS_REORDER register bits are located in the JESD digital page, register 032h (bits 7-0). (9) The BUS_REORDER EN1 register bit is located in the main digital page, register 052h (bit 7). (10) The BUS_REORDER EN2 register bit is located in the main digital page, register 072h (bit 3). 8.4.3.4.1 JESD Transmitter Interface Each of the 10-Gbps SERDES JESD transmitter outputs requires ac coupling between the transmitter and receiver. The differential pair must be terminated with 100-Ω resistors as close to the receiving device as possible to avoid unwanted reflections and signal degradation, as shown in Figure 8-22. Receiver VCM Transmission Line, Zo 0.1 PF 0.1 PF Rt = ZO Rt = ZO DA[3:0]P, DB[3:0]P DA[3:0]M, DB[3:0]M Figure 8-22. Output Connection to Receiver ADS54J40 SBAS714C – MAY 2015 – REVISED DECEMBER 2020 www.ti.com 46 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADS54J40 |
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