DAC53608 datasheet(21/46 Pages) TI2

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No power-on reset

Power-on reset

0.70

Undefined

0.00

1.70

1.80

5.50

VDD (V)

Specified supply

voltage range

DAC53608, DAC43608

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SLASEQ4A – OCTOBER 2018 – REVISED DECEMBER 2018

Product Folder Links: DAC53608 DAC43608

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Feature Description (continued)

8.3.1.4 Output Amplifier

The output buffer amplifier generates rail-to-rail voltages on the output, giving a maximum output range of 0 V to

VDD. Equation 1 shows that the full-scale output range of the DAC output is determined by the voltage on the

VREFIN pin

8.3.2 Reference

The DACx3608 requires an external reference to operate. However, the reference pin VREFIN and the supply pin

VDD can be tied together. The reference input pin voltage ranges from 1.8 V to VDD. The typical input impedance

of this pin when all the channels are powered on is 12.5 kΩ.

8.3.3 Power-on-Reset (POR)

The DACx3608 family of devices includes a power-on reset (POR) function that controls the output voltage at

power up. After the VDD supply has been established, a POR event is issued. The POR causes all registers to

initialize to the default values, and communication with the device is valid only after a 5-ms after VDD reaches

DAC operating range. The default value for the DAC data registers is zero-code . The DAC output remains at the

power-up voltage until a valid command is written to a channel.

When the device powers up, a POR circuit sets the device to the default mode. The POR circuit requires specific

VDD levels, as indicated in Figure 55, in order to make sure that the internal capacitors discharge and reset the

device on power up. In order to make sure that a POR occurs, VDD must be less than 0.7 V for at least 1 ms.

When VDD drops to less than 1.7 V but remains greater than 0.7 V (shown as the undefined region), the device

may or may not reset under all specified temperature and power-supply conditions. In this case, initiate a POR.

When VDD remains greater than 1.7 V, a POR does not occur.

Figure 55. Threshold Levels for VDD POR Circuit

8.3.4 Software Reset

A device software reset event is initiated by writing the reserved code 0x1010 to the SW-RST bit in the

TRIGGER register (address 2h).

8.4 Device Functional Modes

The DACx3608 has two modes of operation: normal and power-down.

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