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DAC53608, DAC43608

SLASEQ4A – OCTOBER 2018 – REVISED DECEMBER 2018

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Copyright © 2018, Texas Instruments Incorporated

Electrical Characteristics (continued)

all minimum/maximum specifications at TA = –40°C to +125°C and all typical specification at TA = 25°C, 1.8 V ≤ VDD ≤ 5.5 V,

VREFIN = 2.5 V for VDD ≥ 2.7 V, VREFIN = 1.8 V for VDD ≤ 2.7 V, RL= 5 kΩ to AGND, CL = 200 pF to AGND, and digital inputs at

VDD or AGND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ZO

DC output impedance

DAC at midscale

0.25

Ω

DAC at code 4d

0.25

DAC at code 1016

0.26

DC-

PSRR

Power supply rejection ratio (DC)

DAC at midscale; VDD = 5 V ± 10%

0.25

mV/V

DYNAMIC PERFORMANCE

tsett

Output voltage settling time

1/4 to 3/4 scale and 3/4 to 1/4 scale

settling to 10%FSR, RL = 5 kΩ, CL = 200

pF, VDD = 5.5 V

10

µs

SR

Slew rate

RL = 5 kΩ, CL = 200 pF, VDD = 5.5 V

0.6

V/µs

Power on glitch magnitude

RL = 5 kΩ, CL = 200 pF

110

mV

Vn

Output noise

0.1 Hz to 10 Hz, DAC at midscale, VDD =

5.5 V

40

µVpp

Vn

Output noise

0.1 Hz to 100 kHz bandwidth, DAC at

midscale, VDD = 5.5 V

0.05

mVrms

Vn

Output noise density

measured at 1 kHz, DAC at midscale,

VDD = 5.5 V

0.2

µV/

√Hz

measured at 10 kHz, DAC at midscale,

VDD = 5.5 V

0.2

AC-

PSRR

Power supply rejection ratio (AC)

200 mV 50/60 Hz sine wave

superimposed on power supply voltage,

DAC at midscale

–71

dB

Channel-to-channel AC crosstalk

Full-scale swing on adjacent channel

1.5

nV-s

Channel-to-channel DC crosstalk

Full-scale swing on all channel,

measured channel at zero or full scale

0.05

LSB

Code change glitch impulse

±1 LSB change around mid code

(including feedthrough)

10

nV-s

Code change glitch impulse magnitude

±1 LSB change around mid code

(including feedthrough)

25

mV

VOLTAGE REFERENCE INPUT

Reference input impedance

All channel powered on

12.5

kΩ

Reference input capacitance

50

pF

DIGITAL INPUTS

Digital feedthrough

At SCLK = 1 MHz, DAC output static at

mid scale

20

nV-s

Pin capacitance

Per pin

10

pF

POWER REQUIREMENTS

IVDD

Current flowing into VDD

Normal mode, all DACs at full scale. SPI

static.

3

5

mA

IVDD

Current flowing into VDD

All DACs power-down

50

µA