LM5145 datasheet(28/66 Pages) TI2

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Based on the static specification of peak-to-peak output voltage ripple denoted by ΔVOUT, choose an output

capacitance that is larger than that given by Equation 9.

OUT

ESR

8 F

˜ '

(9)

Figure 9-1 conceptually illustrates the relevant current waveforms during both load step-up and step-down

transitions. As shown, the large-signal slew rate of the inductor current is limited as the inductor current ramps

to match the new load-current level following a load transient. This slew-rate limiting exacerbates the deficit

of charge in the output capacitor, which must be replenished as rapidly as possible during and after the load

step-up transient. Similarly, during and after a load step-down transient, the slew rate limiting of the inductor

current adds to the surplus of charge in the output capacitor that must be depleted as quickly as possible.

load current,

iOUT(t)

IOUT1

IOUT2

'IOUT

tramp

IOUT2

IOUT1

'IOUT

inductor current, iL(t)

load current, iOUT(t)

'QC

OUT

ramp

OUT

Figure 9-1. Load Transient Response Representation Showing COUT Charge Surplus or Deficit

In a typical regulator application of 48-V input to low output voltage (for example, 5 V), the load-off transient

represents the worst case in terms of output voltage transient deviation. In that conversion ratio application, the

steady-state duty cycle is approximately 10% and the large-signal inductor current slew rate when the duty cycle

collapses to zero is approximately –VOUT/L. Compared to a load-on transient, the inductor current takes much

longer to transition to the required level. The surplus of charge in the output capacitor causes the output voltage

to significantly overshoot. In fact, to deplete this excess charge from the output capacitor as quickly as possible,

the inductor current must ramp below its nominal level following the load step. In this scenario, a large output

capacitance can be advantageously employed to absorb the excess charge and limit the voltage overshoot.

To meet the dynamic specification of output voltage overshoot during such a load-off transient (denoted as

ΔVOVERSHOOT with step reduction in output current given by ΔIOUT), the output capacitance should be larger than

OUT

OVERSHOOT

OUT

˜ '

(10)

The ESR of a capacitor is provided in the manufacturer’s data sheet either explicitly as a specification or

implicitly in the impedance vs. frequency curve. Depending on type, size and construction, electrolytic capacitors

have significant ESR, 5 mΩ and above, and relatively large ESL, 5 nH to 20 nH. PCB traces contribute some

parasitic resistance and inductance as well. Ceramic output capacitors, on the other hand, have low ESR and

LM5146

SNVSBV0A – JUNE 2021 – REVISED JUNE 2021

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