LM5145 datasheet(47/66 Pages) TI2

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11 Layout

11.1 Layout Guidelines

Proper PCB design and layout is important in a high-current, fast-switching circuits (with high current and voltage

slew rates) to assure appropriate device operation and design robustness. As expected, certain issues must

be considered before designing a PCB layout using the LM5146. The high-frequency power loop of the buck

converter power stage is denoted by #1 in the shaded area of Figure 11-1. The topological architecture of a buck

converter means that particularly high di/dt current flows in the components of loop 1, and it becomes mandatory

to reduce the parasitic inductance of this loop by minimizing its effective loop area. Also important is the gate

drive loops of the low-side and high-side MOSFETs, denoted by 2 and 3, respectively, in Figure 11-1.

BST

VCC

PGND

VIN

VOUT

GND

LM5146

VCC

Low-side

gate driver

High-side

gate driver

CVCC

CBST

CIN

COUT

High frequency

power loop

Figure 11-1. DC/DC Regulator Ground System With Power Stage and Gate Drive CirCuit Switching Loops

11.1.1 Power Stage Layout

1. Input capacitors, output capacitors, and MOSFETs are the constituent components of the power stage of a

buck regulator and are typically placed on the top side of the PCB (solder side). The benefits of convective

heat transfer are maximized because of leveraging any system-level airflow. In a two-sided PCB layout,

small-signal components are typically placed on the bottom side (component side). insert at least one inner

plane, connected to ground, to shield and isolate the small-signal traces from noisy power traces and lines.

2. The DC/DC converter has several high-current loops. Minimize the area of these loops in order to suppress

generated switching noise and parasitic loop inductance and optimize switching performance.

• Loop #1: The most important loop to minimize the area of is the path from the input capacitor or

capacitors through the high- and low-side MOSFETs, and back to the capacitor or capacitors through the

ground connection. Connect the input capacitor or capacitors negative terminal close to the source of the

low-side MOSFET (at ground). Similarly, connect the input capacitor or capacitors positive terminal close

to the drain of the high-side MOSFET (at VIN). Refer to loop #1 of Figure 11-1.

• Another loop, not as critical though as loop #1, is the path from the low-side MOSFET through the

inductor and output capacitor(s), and back to source of the low-side MOSFET through ground. Connect

the source of the low-side MOSFET and negative terminal of the output capacitor or capacitors at ground

as close as possible.

3. The PCB trace defined as SW node, which connects to the source of the high-side (control) MOSFET, the

drain of the low-side (synchronous) MOSFET and the high-voltage side of the inductor, must be short and

wide. However, the SW connection is a source of injected EMI and thus must not be too large.

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LM5146

SNVSBV0A – JUNE 2021 – REVISED JUNE 2021

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