LM5145 datasheet(48/66 Pages) TI2

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4. Follow any layout considerations of the MOSFETs as recommended by the MOSFET manufacturer,

including pad geometry and solder paste stencil design.

5. The SW pin connects to the switch node of the power conversion stage and acts as the return path for the

high-side gate driver. The parasitic inductance inherent to loop #1 in Figure 11-1 and the output capacitance

(COSS) of both power MOSFETs form a resonant circuit that induces high frequency (> 100 MHz) ringing

on the SW node. The voltage peak of this ringing, if not controlled, can be significantly higher than the

input voltage. Ensure that the peak ringing amplitude does not exceed the absolute maximum rating limit

for the SW pin. In many cases, a series resistor and capacitor snubber network connected from the SW

node to GND damps the ringing and decreases the peak amplitude. Provide provisions for snubber network

components in the PCB layout. If testing reveals that the ringing amplitude at the SW pin is excessive, then

include snubber components as needed.

11.1.2 Gate Drive Layout

The LM5146 high-side and low-side gate drivers incorporate short propagation delays, adaptive dead-time

control and low-impedance output stages capable of delivering large peak currents with very fast rise and

fall times to facilitate rapid turnon and turnoff transitions of the power MOSFETs. Very high di/dt can cause

unacceptable ringing if the trace lengths and impedances are not well controlled.

Minimization of stray or parasitic gate loop inductance is key to optimizing gate drive switching performance,

whether it be series gate inductance that resonates with MOSFET gate capacitance or common source

inductance (common to gate and power loops) that provides a negative feedback component opposing the

gate drive command, thereby increasing MOSFET switching times. The following loops are important:

• Loop 2: high-side MOSFET, Q1. During the high-side MOSFET turnon, high current flows from the bootstrap

(boot) capacitor through the gate driver and high-side MOSFET, and back to the negative terminal of the boot

capacitor through the SW connection. Conversely, to turn off the high-side MOSFET, high current flows from

the gate of the high-side MOSFET through the gate driver and SW, and back to the source of the high-side

MOSFET through the SW trace. Refer to loop #2 of Figure 11-1.

• Loop 3: low-side MOSFET, Q2. During the low-side MOSFET turn-on, high current flows from the VCC

decoupling capacitor through the gate driver and low-side MOSFET, and back to the negative terminal of the

capacitor through ground. Conversely, to turn off the low-side MOSFET, high current flows from the gate of

the low-side MOSFET through the gate driver and GND, and back to the source of the low-side MOSFET

through ground. Refer to loop #3 of Figure 11-1.

TI strongly recommends following circuit layout guidelines when designing with high-speed MOSFET gate drive

circuits.

1. Connections from gate driver outputs, HO and LO, to the respective gate of the high-side or low-side

MOSFET must be as short as possible to reduce series parasitic inductance. Use 0.65 mm (25 mils) or wider

traces. Use a via or vias, if necessary, of at least 0.5 mm (20 mils) diameter along these traces. Route HO

and SW gate traces as a differential pair from the LM5146 to the high-side MOSFET, taking advantage of

flux cancellation.

2. Minimize the current loop path from the VCC and BST pins through their respective capacitors as these

provide the high instantaneous current, up to 3.5 A, to charge the MOSFET gate capacitances. Specifically,

locate the bootstrap capacitor, CBST, close to the BST and SW pins of the LM5146 to minimize the area of

loop #2 associated with the high-side driver. Similarly, locate the VCC capacitor, CVCC, close to the VCC and

PGND pins of the LM5146 to minimize the area of loop #3 associated with the low-side driver.

3. Placing a 2-Ω to 10-Ω resistor in series with the boot capacitor, as shown in Figure 9-16, slows down the

high-side MOSFET turn-on transition, serving to reduce the voltage ringing and peak amplitude at the SW

node at the expense of increased MOSFET turnon power loss.

11.1.3 PWM Controller Layout

With the proviso to locate the controller as close as possible to the MOSFETs to minimize gate driver trace runs,

the components related to the analog and feedback signals, current limit setting, and temperature sense are

considered in the following:

1. Separate power and signal traces, and use a ground plane to provide noise shielding.

LM5146

SNVSBV0A – JUNE 2021 – REVISED JUNE 2021

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