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NormalMode

LRCK

L

Sub-frame0 Sub-frame1

OneFrame,1/f

S

Sub-frame2 Sub-frame3

R

L

R

L

R

L

R

L

Sub-frame0 Sub-frame1

OneFrame,1/f

S

OneFrame,1/f

S

Sub-frame0 Sub-frame1

R

L

R

L

R

L

R

L

OneFrame OneFrame

1/f

S

1/f

S

1/f

S

1/f

S

OneFrame OneFrame

R

L

R

L

R

L

R

DATA

LRCK

DATA

LRCK

DATA

DoubleSpeedMode

QuadSpeedMode

DIGITAL DECIMATION FILTER

DIGITAL HIGH-PASS FILTER

PCM4222

SBAS399A – OCTOBER 2006 – REVISED MARCH 2007

Each L or R channel time slot is 32-bits long, with 24-bit data Left-Justified in the time slot. Audio data is MSB first.

Sub-frame assignments for each PCM4222 device are selected by the corresponding SUB0 and SUB1 pin settings.

Figure 45. TDM Data Formats: Master Mode

The PCM4222 digital decimation filter is a linear phase, multistage finite impulse response (FIR) design with two

user-selectable filter responses. The decimation filter provides the digital downsampling and low-pass anti-alias

filter functions for the PCM4222.

The Classic filter response is typical of traditional audio data converters, with Figure 26 through Figure 29

detailing the frequency response, and the related specifications given in the Electrical Characteristics table. The

group delay for the Classic filter is 39/fS, or 812.5µs for fS = 48kHz and 406.25µs for fS = 96kHz. The Classic

filter response is not available for the Quad Speed sampling mode.

The Low Group Delay response provides a lower latency option for the decimation filter, and is detailed in

Figure 30 through Figure 33, with the relevant specifications given in the Electrical Characteristics table. The

Low Group Delay filter response is available for all sampling modes. The group delay for this filter is 21/fS, or

437.5

µs for f

S = 48kHz, 218.75µs for fS = 96kHz, and 109.375µs for fS = 192kHz.

The decimation filter response is selected using the DF input (pin 21), with the settings summarized in Table 5.

For Quad Speed sampling mode operation, the Low Group Delay filter is always selected, regardless of the DF

pin setting.

Table 5. Decimation Filter Response Selection

DF (pin 21)

DECIMATION FILTER RESPONSE

LO

Classic response, with group delay = 39/fS

HI

Low Group Delay response, with group delay = 21/fS

The PCM4222 incorporates digital high-pass filters for both the left and right audio channels, with the purpose of

removing the

∆Σ modulator dc offset from the audio output data. Figure 34 and Figure 35 detail the frequency

response for the digital high-pass filter. The f–3dB frequency is approximately fS/48000, where fS is the PCM

output sampling rate.

Two inputs, HPFDR (pin 17) and HPFDL (pin 18), allow the digital high-pass filter to be enabled or disabled

individually for the right and left channels, respectively. Table 6 summarizes the operation of the high-pass filter

disable pins.

24

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