PCM4222 datasheet(34/44 Pages) TI2

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PCM4222

Dividedby2

MCKI

BCK

LRCK

DIX4192

SRC4392

512f (Normal)

256f (DoubleSpeed)

128f (QuadSpeed)

Master

Clock

MCLK

DATA

BCKA

LRCKA

SDINA

PCM4222

SBAS399A – OCTOBER 2006 – REVISED MARCH 2007

VDDPCM4222 = VIODIX4192 or SRC4392.

Audio data format if I2S or Left Justified.

Interface supports ADC Slave or Master configurations, depending on DIX4192, SRC4382, or SRC4392 register

setup.

Figure 54. Interfacing the PCM4222 to a DIT4192, SRC4382, or SRC4392

Table 12. Register Configuration Sequence for an ADC Master Mode Interface

COMMENTS

Select Register Page 0

Port A is Slave mode with Left-Justified audio data format, or

Port A is Slave mode with I2S Data format

Default for Port A Slave mode operation

Divide MCLK by 512 for Normal sampling,or

Divide MCLK by 256 for Double Speed Sampling, or

Divide MCLK by 128 for Quad Speed sampling

Line Driver and AESOUT buffer enabled

Data buffers on Register Page 2 are the source for the DIT

channel status (C) and user (U) data

Power up Port A and the DIT

Table 13. Register Configuration Sequence for an ADC Slave Mode Interface

COMMENTS

Select Register Page 0

Port A is Master mode with Left-Justified audio data format, or

Port A is Master mode with I2S Data format

Divide MCLK by 512 for Normal sampling, or

Divide MCLK by 256 for Double Speed sampling, or

Divide MCLK by 128 for Quad Speed sampling

Divide MCLK by 512 for Normal sampling,or

Divide MCLK by 256 for Double Speed Sampling, or

Divide MCLK by 128 for Quad Speed sampling

Line Driver and AESOUT buffer enabled

Data buffers on Register Page 2 are the source for the DIT

channel status (C) and user (U) data

Power up Port A and the DIT

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