THS4541IRUNR.B datasheet(31/66 Pages) TI2

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7.6 Factors Influencing Harmonic Distortion

As shown in the swept frequency harmonic distortion plots, the THS4541 provides extremely low distortion at

lower frequencies. In general, FDA output harmonic distortion mainly relates to the open-loop linearity in the

output stage corrected by the loop gain at the fundamental frequency. Figure 6-16 and Figure 6-34 shows that

as the total load impedance decreases (including the effect of the feedback resistor elements in parallel for

loading purposes), the output-stage, open-loop linearity degrades, increasing the harmonic distortion. Figure

6-14 and Figure 6-32 shows that as the output voltage swings increase, very fine-scale, open-loop, output-stage

nonlinearities increase, also degrading the harmonic distortion. Conversely, decreasing the target output voltage

swings drops the distortion terms rapidly. For harmonic-distortion testing, 2 VPP is used as a nominal swing

because this value represents a typical ADC, full-scale, differential input range.

Figure 6-18 and Figure 6-36 shows how increasing the gain acts to decrease the loop gain, resulting in the

increasing harmonic distortion terms. One advantage to the capacitive compensation for the attenuator design

(described in the typical application example of Section 9.2.1) is that the noise gain is shaped up with frequency

to achieve a crossover at an acceptable phase margin at higher frequencies. This compensation holds the loop

gain high at frequencies lower than the noise-gain zero, improving distortion in these lower bands.

Anything that moves the output pin voltage swings close to clipping into the supplies rapidly degrades harmonic

distortion. Output clipping can occur from either absolute differential swing, or the swing can be moved closer to

the supplies with the common-mode control. Figure 6-17 and Figure 6-35 shows this effect.

The THS4541 does an exceptional job of converting from single-ended inputs to differential outputs with very

low harmonic distortions. External resistors of 1% tolerance are used in characterization with good results.

Imbalancing the feedback divider ratios does not degrade distortion directly. Imbalanced feedback ratios convert

common-mode inputs to differential mode at the outputs with the gain described in Section 7.4.

7.7 Driving Capacitive Loads

Figure 6-8 and Figure 6-26 shows a very common requirement is driving the capacitive load of an ADC or some

other next stage device. Directly driving a capacitive load with a closed-loop amplifier such as the THS4541 can

lead to an unstable response, as shown in the step response plots into a capacitive load. Figure 7-11 shows how

one typical remedy for this instability is to add two small series resistors (Ro) at the outputs of the THS4541.

Figure 6-6 and Figure 6-24 provide parametric plots of recommended Ro values versus differential capacitive

load values and gain.

Rf1

402

Rload

500

Rg1

191

Rg2

191

60.2

Output

Measurement

Point

THS4541 Wideband,

Fully-Differential Amplifier

50-

Input Match,

Gain of 2 V/V from Rt,

Single-Ended Source to

Differential Output

Vocm

Rf2

402

Vcc

Vocm

Vcc

FDA

Ro1

Ro2

Cload

22 pF

50-

Source

Figure 7-11. Including Ro When Driving Capacitive Loads

Operating at higher gains requires lower Ro values to achieve a ±0.5-dB flat response for the same capacitive

load. Figure 6-6 and Figure 6-24 (where the Ro value is 0 Ω) shows how some direct parasitic loading is

acceptable with no series Ro that increases with gain setting. Even when these plots suggest no series Ro

is required, good practice is to include a place for the Ro elements in the board layout (0-Ω load initially) for

later adjustment, in case the response appears unacceptable. The TINA simulation model does a good job of

predicting this effect and showing the impact for different choices of capacitive load isolating resistors (Ro).

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THS4541

SLOS375B – AUGUST 2014 – REVISED FEBRUARY 2024

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