THS4541IRUNR.B datasheet(46/66 Pages) TI2

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9.2.1.2 Detailed Design Procedure

Operating the THS4541 at a low dc noise gain, or with higher feedback resistors, can cause a lower phase

margin to exist, giving the response peaking shown in Figure 6-1 for the gain of 0.1 (a 1/10 attenuator) condition.

Although often useful operating the THS4541 as an attenuator (taking a large input range to a purely differential

signal around a controlled-output, common-mode voltage), the response peaking illustrated in Figure 6-1 is

usually undesirable. Several methods can be used to reduce or eliminate this peaking; usually, at the cost of

higher output noise. Using DC techniques always increases the output noise broadband, while using an ac

noise-gain-shaping technique peaks the noise, but only at higher frequencies that can then be filtered off with the

typical passive filters often used after this stage. Figure 9-1 shows a simplified schematic for the gain of 0.1 V/V

test from Figure 7-1.

This configuration shows a nominal 18° phase margin (from Table 7-2); therefore, a very highly-peaked response

is illustrated in Figure 6-1. This peaking can be eliminated by placing two feedback capacitors across the Rf

elements and a differential input capacitor. Adding these capacitors provides a transition from a resistively set

noise gain (NG1 here; 1.1 in Table 7-2) to a capacitive divider at high-frequency flattening out to a higher noise

gain (NG2 here). The key for this approach is to target a Zo, where the noise gain begins to peak up. Using only

the following terms, and targeting a closed-loop flat (Butterworth) response, gives this solution sequence for Zo

and then the capacitor values.

1. Gain bandwidth product in Hz (850 MHz for the THS4541)

2. Low frequency noise gain, NG1 ( = 1.1 in the attenuator gain of 0.1 V/V design)

3. Target high-frequency noise gain selected to be higher than NG1 (NG2 = 3.1 V/V is selected for this design)

4. Feedback resistor value, Rf (assumed balanced for this differential design = 402 Ω for this design example)

From these elements, for any decompensated voltage-feedback op amp or FDA, solve for Zo (in Hz) using

Equation 15:

GBP

NG1

NG2

NG1

(15)

From this target zero frequency in the noise gain, solve for the feedback capacitors using Equation 16:

‡

NG2

(16)

The next step is to resolve the input capacitance on the summing junction. Equation 17 is for a single-ended

op amp (for example, OPA847) where that capacitor goes to ground. To use Equation 17 for a voltage-feedback

FDA, cut the target value in half, and place the result across the two inputs (reducing the external value by the

specified internal differential capacitance).

NG2

1 Cf

(17)

Setting the external compensation elements using Equation 15 to Equation 17 allows an estimate of the resulting

flat bandwidth f–3dB frequency, as shown in Equation 18:

‡

3dB

GBP

(18)

Running through these steps for the THS4541 in the attenuator circuit of Figure 9-1 gives the proposed

compensation of Figure 9-2 where Equation 18 estimates a bandwidth of 252 MHz (Zo target is 74.7 MHz).

THS4541

SLOS375B – AUGUST 2014 – REVISED FEBRUARY 2024

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