LM5171 datasheet(39/89 Pages) TI2

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tHD;DAT;MAX

tSU;DAT;MAX

SDA

SCL

Figure 7-3. I 2 C Data Transmission Timing for maximum rise/fall times.

7.3 Clock Stretching

Clock stretching is not supported. If the device is addressed while busy and not able to process the received

data, it does not acknowledge the transaction.

7.4 Data Transfer Formats

The device supports four different read/write operations:

• Single read from a defined register address.

• Single write to a defined register address.

• Sequential read starting from a defined register address

• Sequential write starting from a defined register address

7.5 Single READ From a Defined Register Address

Figure 7-4 shows the format of a single read from a defined register address. First, the Controller issues a start

condition followed by a seven-bit I 2 C address. Next, the Controller writes a zero to signify that a write operation

is conducted. Upon receiving an acknowledge from the Peripheral the Controller sends the eight-bit register

address across the bus. Following a second acknowledge the device sets the internal I 2 C register number to

the defined value. Then the Controller issues a repeat start condition and the seven-bit I 2 C address followed

by a one to signify that a read operation has conducted. Upon receiving a third acknowledge, the Controller

releases the bus to the device. The device then returns the eight-bit data value from the register on the bus. The

Controller does not acknowledge (nACK) and issues a stop condition. This action concludes the register read.

7-bit target Address

8-bit Register Address

write

From controller to target

From target to controller

Start

Acknowlege

Stop

Not Acknowlege

7-bit target Address

DATA

REGADDR

read

Figure 7-4. Single READ From a Defined Register Address

7.6 Sequential READ Starting From a Defined Register Address

A sequential read operation is an extension of the single read protocol and shown in Figure 7-5. The Controller

acknowledges the reception of a data byte, the device auto increments the register address and returns the data

from the next register. The data transfer is stopped by the Controller not acknowledging the last data byte and

sending a stop condition.

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LM5171-Q1

SNVSC75B – APRIL 2023 – REVISED SEPTEMBER 2025

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