LM5171 datasheet(13/89 Pages) TI2

13 / 89 page

5.6 Timing Requirements (continued)

Over operating junction temperature range and recommended supply voltage range (unless otherwise noted)

MIN

NOM

MAX

UNI

tHIGH

HIGH period of the SCL clock

Standard mode

4.0

µs

Fast mode

0.6

Fast mode plus (1)

0.26

tBUF

Bus free time between a STOP and

a START condition

Standard mode

4.7

µs

Fast mode

1.3

Fast mode plus (1)

0.5

tSU:STA

Set-up time for a repeated START

condition

Standard mode

4.7

µs

Fast mode

0.6

Fast mode plus (1)

0.26

tHD:STA

Hold time (repeated) START

condition

Standard mode

4.0

µs

Fast mode

0.6

Fast mode plus (1)

0.26

tHD:DAT

Data hold time

Standard mode

µs

Fast mode

Fast mode plus (1)

Rise time of both SDA and SCL

signals

Standard mode

1000

Fast mode

300

Fast mode plus (1)

Fall time of both SDA and SCL

signals

Standard mode

300

Fast mode

20×VDD/

5.5

300

Fast mode plus (1)

20×VDD/

5.5

120

tsu:STO

Set-up time for STOP condition

Standard mode

4.0

µs

Fast mode

0.6

Fast mode plus (1)

0.26

tVD;DAT

Data valid time

Standard mode

3.45

µs

Fast mode

0.9

Fast mode plus (1)

0.45

tVD;ACK

Data valid acknowledge time

Standard mode

3.45

µs

Fast mode

0.9

Fast mode plus (1)

0.45

Capacitive load for each bus line

Standard mode

400

Fast mode

400

(1)

Fast mode plus is supported but not fully compliant with I2C standard

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LM5171-Q1

SNVSC75B – APRIL 2023 – REVISED SEPTEMBER 2025

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